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Advance Information
MPC8280EC/D Rev. 0.2, 11/2002 MPC8280 Hardware Specifications
This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for .13m (HiP7) members of the PowerQUICC IITM family of integrated communications processors--the MPC8280 and the MPC8270 (collectively referred to throughout this document as the MPC8280). The following topics are addressed: Topic Section 1.1, "Features" Section 1.2, "Electrical and Thermal Characteristics" Section 1.2.1, "DC Electrical Characteristics" Section 1.2.2, "Thermal Characteristics" Section 1.2.3, "AC Electrical Characteristics" Section 1.3, "Clock Configuration Modes" Section 1.3.1, "Local Bus Mode" Section 1.3.2, "PCI Mode" Section 1.4, "Pinout" Section 1.5, "Package Description" Section 1.6, "Ordering Information" Page 2 6 6 10 11 18 18 21 35 63 66
HiP7 members of the PowerQUICC IITM family are available in two packages--the standard ZU package and an alternate VR package--as shown in Table 1. For more information on VR packages, contact your Motorola sales office. Note that throughout this document references to the MPC8280 are inclusive of VR-package devices unless otherwise specified.
Table 1. HiP7 PowerQUICC II Device Packages
ZU (480 TBGA) MPC8280 -- MPC8270 VR (516 PBGA) -- MPC8275VR MPC8270VR
PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Features
Figure 1 shows the block diagram for the MPC8280. Shaded portions are device- or package-specific; refer to the notes below.
16 Kbytes I-Cache I-MMU G2 Core System Interface Unit (SIU) 16 Kbytes D-Cache D-MMU Bus Interface Unit 60x-to-PCI Bridge 60x-to-Local Bridge Memory Controller Serial DMAs 4 Virtual IDMAs Clock Counter System Functions 60x Bus
PCI Bus
32 bits, up to 66 MHz or
Local Bus4
32 bits, up to 100 MHz
Communication Processor Module (CPM) Timers Parallel I/O Baud Rate Generators Interrupt Controller 32 KB Instruction RAM 32 KB Data RAM
32-bit RISC Microcontroller and Program ROM
IMA 1 Microcode
MCC11
MCC2
FCC1
FCC2
FCC3
SCC1
SCC2
SCC3
SCC4/ USB
SMC1
SMC2
SPI
I2C
TC Layer Hardware1
Time Slot Assigner Serial Interface
8 TDM Ports2
3 MII orRMII Ports
2 UTOPIA Ports3
Non-Multiplexed I/O
Notes: 1 MPC8280 only (not on MPC8270 nor the VR package (MPC8270VR and MPC8275VR)) 2 MPC8280 only (4 TDMs on MPC8270 and the VR package (MPC8270VR and MPC8275VR)) 3 MPC8280 and MPC8275VR only (not on MPC8270 nor MPC8270VR) 4 No local bus on the VR package (MPC8270VR and MPC8275VR)
Figure 1. MPC8280 Block Diagram
1.1
*
Features
Dual-issue integer (G2) core -- A core version of the EC603e microprocessor -- System core microprocessor supporting frequencies of 150-450 MHz -- Separate 16-Kbyte data and instruction caches: - Four-way set associative - Physically addressed - LRU replacement algorithm -- PowerPC architecture-compliant memory management unit (MMU) -- Common on-chip processor (COP) test interface
The major features of the MPC8280 are as follows:
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MPC8280 Hardware Specifications
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Features
* *
*
*
*
-- High-performance (855 Dhrystones MIPS at 450 MHz) -- Supports bus snooping for data cache coherency -- Floating-point unit (FPU) Separate power supply for internal logic and for I/O Separate PLLs for G2 core and for the CPM -- G2 core and CPM can run at different frequencies for power/performance optimization -- Internal core/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 6:1, 7:1, 8:1 ratios -- Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1 ratios 64-bit data and 32-bit address 60x bus -- Bus supports multiple master designs -- Supports single- and four-beat burst transfers -- 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller -- Supports data parity or ECC and address parity 32-bit data and 18-bit address local bus -- Single-master bus, supports external slaves -- Eight-beat burst transfers -- 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller 60x-to-PCI bridge -- Programmable host bridge and agent -- 32-bit data bus, 66.67/83.3/100 MHz, 3.3 V -- Synchronous and asynchronous 60x and PCI clock modes -- All internal address space available to external PCI host -- DMA for memory block transfers -- PCI-to-60x address remapping
*
PCI bridge -- PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz -- On-chip arbitration -- Support for PCI-to-60x-memory and 60x-memory-to-PCI streaming -- PCI Host Bridge or Peripheral capabilities -- Includes 4 DMA channels for the following transfers: - PCI-to-60x to 60x-to-PCI - 60x-to-PCI to PCI-to-60x - PCI-to-60x to PCI-to-60x - 60x-to-PCI to 60x-to-PCI -- Includes all of the configuration registers (which are automatically loaded from the EPROM and used to configure the MPC8280) required by the PCI standard as well as message and doorbell registers -- Supports the I2O standard -- Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0
MOTOROLA
MPC8280 Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
3
Features
August 3, 1998) -- Support for 66.67/83.33/100 MHz, 3.3 V specification -- 60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port -- Makes use of the local bus signals, so there is no need for additional pins * System interface unit (SIU) -- Clock synthesizer -- Reset controller -- Real-time clock (RTC) register -- Periodic interrupt timer -- Hardware bus monitor and software watchdog timer -- IEEE 1149.1 JTAG test access port * Twelve-bank memory controller -- Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other userdefinable peripherals -- Byte write enables and selectable parity generation -- 32-bit address decodes with programmable bank size -- Three user programmable machines, general-purpose chip-select machine, and page-mode pipeline SDRAM machine -- Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local) -- Dedicated interface logic for SDRAM * * CPU core can be disabled and the device can be used in slave mode to an external core Communications processor module (CPM) -- Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications protocols -- Interfaces to G2 core through an on-chip 32-Kbyte dual-port data RAM, an on-chip 32-Kbyte dual-port instruction RAM and DMA controller -- Serial DMA channels for receive and transmit on all serial channels -- Parallel I/O registers with open-drain and interrupt capability -- Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers -- Three fast communications controllers supporting the following protocols: - 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent interface (MII) or reduced media independent interface (RMII) - ATM--Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 16 K external connections (no ATM support for the MPC8270) - Transparent - HDLC--Up to T3 rates (clear channel) - FCC2 can also be connected to the TC layer (MPC8280 only) -- Two multichannel controllers (MCCs) (one MCC on the MPC8270) - Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. Each MCC can be split
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MPC8280 Hardware Specifications
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Features
into four subgroups of 32 channels each. - Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces up to four TDM interfaces per MCC -- Four serial communications controllers (SCCs) identical to those on the MPC860, supporting the digital portions of the following protocols: - Ethernet/IEEE 802.3 CDMA/CS - HDLC/SDLC and HDLC bus - Universal asynchronous receiver transmitter (UART) - Synchronous UART - Binary synchronous (BISYNC) communications - Transparent -- Universal serial bus (USB) controller--supports both host and slave modes -- Two serial management controllers (SMCs), identical to those of the MPC860 - Provide management for BRI devices as general circuit interface (GCI) controllers in timedivision-multiplexed (TDM) channels - Transparent - UART (low-speed operation) -- One serial peripheral interface identical to the MPC860 SPI -- One inter-integrated circuit (I2C) controller (identical to the MPC860 I2C controller) - Microwire compatible - Multiple-master, single-master, and slave modes -- Up to eight TDM interfaces (four on the MPC8270) - Supports two groups of four TDM channels for a total of eight TDMs (one group of four on the MPC8270) - 2,048 bytes of SI RAM - Bit or byte resolution - Independent transmit and receive routing, frame synchronization - Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), and user-defined TDM serial interfaces -- Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs, SCCs, SMCs, and serial channels -- Four independent 16-bit timers that can be interconnected as two 32-bit timers Inverse multiplexing for ATM capabilities (IMA) (MPC8280 only).Supported by eight transfer transmission convergence (TC) layers between the TDMs and FCC2. Transmission convergence (TC) layer (MPC8280 only)
* *
MOTOROLA
MPC8280 Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
5
Electrical and Thermal Characteristics
1.2
1.2.1
Electrical and Thermal Characteristics
DC Electrical Characteristics
This section provides AC and DC electrical specifications and thermal characteristics for the MPC8280.
This section describes the DC electrical characteristics for the MPC8280. Table 2 shows the maximum electrical ratings.
Table 2. Absolute Maximum Ratings1
Rating Core supply voltage2 PLL supply I/O supply voltage2 Symbol VDD VCCSYN VDDH VIN Tj TSTG Value -0.3 - 2.25 -0.3 - 2.25 -0.3 - 4.0 GND(-0.3) - 3.6 120 (-55) - (+150) Unit V V V V C C
voltage3
Input voltage4 Junction temperature Storage temperature range
1
Absolute maximum ratings are stress ratings only; functional operation (see Table 3) at the maximums is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage. 2 Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset. 3 Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH should not exceed VDD/VCCSYN by more than 2.5 V during normal operation. 4 Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.
Table 3 lists recommended operational voltage conditions.
Table 3. Recommended Operating Conditions1
Rating Core supply voltage PLL supply voltage I/O supply voltage Input voltage Junction temperature (maximum) Ambient temperature
1
Symbol VDD VCCSYN VDDH VIN Tj TA
Value 1.425 - 1.575 1.425 - 1.575 3.135 - 3.465 GND (-0.3) - 3.465 1052 0-702
Unit V V V V C C
Caution: These are the recommended and tested operating conditions. Proper operation outside of these conditions is not guaranteed. 2 Note that for extended temperature parts the range is (-40) - 105 . T Tj
A
NOTE VDDH and VDD must track each other and both must vary in the same direction--in the positive direction (+0.165 VDDH and +0.075 VDD) or in the negative direction (-0.165 VDDH and -0.075 VDD).
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MPC8280 Hardware Specifications
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Electrical and Thermal Characteristics
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (either GND or VCC). Table 4 shows DC electrical characteristics.
Table 4. DC Electrical Characteristics
Characteristic Input high voltage, all inputs except CLKIN Input low voltage CLKIN input high voltage CLKIN input low voltage Input leakage current, VIN = VDDH1 = VDDH1 Symbol VIH VIL VIHC VILC IIN IOZ IL IH VOH Min 2.0 GND 2.4 GND -- -- -- -- 2.4 Max 3.465 0.8 3.465 0.4 10 10 1 1 -- Unit V V V V A A A A V
Hi-Z (off state) leakage current, VIN Signal low input current, VIL = 0.8 V
Signal high input current, VIH = 2.0 V Output high voltage, IOH = -2 mA except UTOPIA mode, and open drain pins In UTOPIA mode2 (UTOPIA pins only): IOH = -8.0mA PA[0-31] PB[4-31] PC[0-31] PD[4-31] In UTOPIA mode2 (UTOPIA pins only): IOL = 8.0mA PA[0-31] PB[4-31] PC[0-31] PD[4-31]
VOL
--
0.5
V
MOTOROLA
MPC8280 Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Electrical and Thermal Characteristics Table 4. DC Electrical Characteristics (Continued)
Characteristic IOL = 7.0mA BR BG ABB/IRQ2 TS A[0-31] TT[0-4] TBST TSIZE[0-3] AACK ARTRY DBG DBB/IRQ3 D[0-63] DP(0)/RSRV/EXT_BR2 DP(1)/IRQ1/EXT_BG2 DP(2)/TLBISYNC/IRQ2/EXT_DBG2 DP(3)/IRQ3/EXT_BR3/CKSTP_OUT DP(4)/IRQ4/EXT_BG3/CORE_SREST DP(5)/TBEN/IRQ5/EXT_DBG3 DP(6)/CSE(0)/IRQ6 DP(7)/CSE(1)/IRQ7 PSDVAL TA TEA GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5 CPU_DBG CPU_BR IRQ0/NMI_OUT IRQ7/INT_OUT/APE PORESET HRESET SRESET RSTCONF QREQ Symbol VOL Min -- Max 0.4 Unit V
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MPC8280 Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics Table 4. DC Electrical Characteristics (Continued)
Characteristic IOL = 5.3mA CS[0-9] CS(10)/BCTL1 CS(11)/AP(0) BADDR[27-28] ALE BCTL0 PWE[0-7]/PSDDQM[0-7]/PBS[0-7] PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 LWE[0-3]LSDDQM[0-3]/LBS[0-3]/PCI_CFG[0-3] LSDA10/LGPL0/PCI_MODCKH0 LSDWE/LGPL1/PCI_MODCKH1 LOE/LSDRAS/LGPL2/PCI_MODCKH2 LSDCAS/LGPL3/PCI_MODCKH3 LGTA/LUPMWAIT/LGPL4/LPBS LSDAMUX/LGPL5/PCI_MODCK LWR MODCK1/AP(1)/TC(0)/BNKSEL(0) MODCK2/AP(2)/TC(1)/BNKSEL(1) MODCK3/AP(3)/TC(2)/BNKSEL(2) IOL = 3.2mA L_A14/PAR L_A15/FRAME/SMI L_A16/TRDY L_A17/IRDY/CKSTP_OUT L_A18/STOP L_A19/DEVSEL L_A20/IDSEL L_A21/PERR L_A22/SERR L_A23/REQ0 L_A24/REQ1/HSEJSW L_A25/GNT0 L_A26/GNT1/HSLED L_A27/GNT2/HSENUM L_A28/RST/CORE_SRESET L_A29/INTA L_A30/REQ2 L_A31 LCL_D(0-31)/AD(0-31) LCL_DP(0-3)/C/BE(0-3) PA[0-31] PB[4-31] PC[0-31] PD[4-31] TDO
1
Symbol VOL
Min --
Max 0.4
Unit V
The leakage current is measured for nominal VDDH and VDD or both VDDH and VDD must vary in the same direction--VDDH and VDD must both vary in the positive direction (+0.165 VDDH and +0.075 VDD) or both vary in the negative direction (-0.165 VDDH and -0.075 VDD). 2 MPC8280 only.
MOTOROLA
MPC8280 Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Electrical and Thermal Characteristics
1.2.2
Thermal Characteristics
Table 5 describes thermal characteristics for both the packages. Refer to Table 1 for information on a given device's package.
Table 5. Thermal Characteristics
Value Characteristic Symbol 480 TBGA (ZU package) 13.07 JA 9.55 10.48 JA 7.78 516 PBGA (VR package) 27 21 19 16 C/W C/W Unit Air Flow
Junction to ambient-- single-layer board1 Junction to ambient-- four-layer board
1
Natural convection 1 m/s Natural convection 1 m/s
Assumes no thermal vias
1.2.2.1
Layout Practices
Each VCC pin should be provided with a low-impedance path to the board's power supply. Each ground pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip. The VCC power supply should be bypassed to ground using at least four 0.1 F by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC and ground should be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes. All output pins on the MPC8280 have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized in order to minimize overdamped conditions and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VCC and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. Table 6 provides preliminary, estimated power dissipation for various configurations. Note that suitable thermal management is required for conditions above PD = 3W (when the ambient temperature is 70 C or greater) to ensure the junction temperature does not exceed the maximum specified value. Also note that the I/O power should be included when determining whether to use a heat sink.
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MPC8280 Hardware Specifications
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Electrical and Thermal Characteristics Table 6. Estimated Power Dissipation for Various Configurations1
CPM Multiplication Factor 3 3.5 4 3 3 3 CPU Multiplication Factor 4.5 5 6 4 4.5 5 PINT(W)2 CPU (MHz) Vddl 1.5 Volts Nominal 83.33 83.33 83.33 100 100 100
1 2
Bus (MHz)
CPM (MHz)
Maximum 1.2 1.3 1.5 1.3 1.45 1.5
250 292 333 300 300 300
350 417 500 400 450 500
1.0 1.1 1.3 1.1 1.2 1.25
Test temperature = room temperature (25 C) PINT = IDD x VDD Watts
1.2.3
AC Electrical Characteristics
The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and inputs for 66.67/83.33/100 MHz MPC8280 devices. Note that AC timings are based on a 50-pf load. Typical output buffer impedances are shown in Table 7.
Table 7. Output Buffer Impedances1
Output Buffers 60x bus Local bus Memory controller Parallel I/O PCI
1
Typical Impedance () 45 45 45 45 25
These are typical values at 65 C. Impedance may vary by 25% with process and temperature.
Table 8 lists CPM output characteristics.
Table 8. AC Characteristics for CPM Outputs1
Spec_num sp36a sp36b sp40 sp38a sp38b sp42 sp43
1
Characteristic FCC outputs-internal clock (NMSI) FCC outputs-external clock (NMSI) TDM outputs/SI SCC/SMC/SPI/I2C outputs-internal clock (NMSI) SCC/SMC/SPI/I2C outputs-external clock (NMSI) PIO/TIMER/DMA outputs COL width high (FCC)
Maximum Delay (ns) Minimum Delay (ns) 5.5 12 12 16 16 11 -- 1 2 3 0.5 2 1 1.5 CLK
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin.
MOTOROLA
MPC8280 Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
11
Electrical and Thermal Characteristics
Table 9 lists CPM input characteristics.
Table 9. AC Characteristics for CPM Inputs1
Spec_num Characteristic Setup (ns) 8 2.5 5 16 4 8 Hold (ns) 0 2 3 0 2 1
sp16a/sp17a FCC inputs-internal clock (NMSI) sp16b/sp17b FCC inputs-external clock (NMSI) sp20/sp21 TDM inputs/SI
sp18a/sp19a SCC/SMC/SPI/I2C inputs-internal clock (NMSI) sp18b/sp19b SCC/SMC/SPI/I2C inputs-external clock (NMSI) sp22/sp23
1
PIO/TIMER/DMA inputs
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin.
NOTE Although the specifications generally reference the rising edge of the clock, the following AC timing diagrams also apply when the falling edge is the active edge. Figure 2 shows the FCC internal clock.
BRG_OUT sp17a sp16a FCC input signals sp36a FCC output signals
Note: When GFMR.TCI = 0
sp36a
FCC output signals
Note: When GFMR.TCI = 1
Figure 2. FCC Internal Clock Diagram
Figure 3 shows the FCC external clock.
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MPC8280 Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
Serial ClKin sp17b sp16b FCC input signals sp36b FCC output signals
Note: When GFMR[TCI] = 0
sp36b FCC output signals
Note: When GFMR[TCI] = 1
Figure 3. FCC External Clock Diagram
Figure 4 shows the SCC/SMC/SPI/I2C external clock.
Serial CLKin sp18b SCC/SMC/SPI/I2C input signals
(See note.)
sp19b
sp38b SCC/SMC/SPI/I2C output signals
(See note.)
Note: The clock edge is selectable on SCC and SPI.
Figure 4. SCC/SMC/SPI/I2C External Clock Diagram
Figure 5 shows the SCC/SMC/SPI/I2C internal clock.
BRG_OUT sp18a SCC/SMC/SPI/I2C input signals
(See note.)
sp19a
sp38a SCC/SMC/SPI/I2C output signals
(See note.)
Note: The clock edge is selectable on SCC and SPI.
Figure 5. SCC/SMC/SPI/I2C Internal Clock Diagram
MOTOROLA
MPC8280 Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Electrical and Thermal Characteristics
Figure 6 shows TDM input and output signals.
Serial CLKin sp20 TDM input signals sp40/sp41 TDM output signals Note: There are four possible TDM timing conditions: 1. Input sampled on the rising edge and output driven on the rising edge (shown). 2. Input sampled on the rising edge and output driven on the falling edge. 3. Input sampled on the falling edge and output driven on the falling edge. 4. Input sampled on the falling edge and output driven on the rising edge. sp21
Figure 6. TDM Signal Diagram
Figure 7 shows PIO and timer signals.
Sys clk
sp23 sp22 PIO/TIMER input signals sp42 TIMER output signals
sp42 PIO output signals
Figure 7. PIO and Timer Signal Diagram
Table 10 lists SIU input characteristics.
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MPC8280 Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics Table 10. AC Characteristics for SIU Inputs1
Setup (ns) Spec_num Characteristic 66 MHz sp11/sp10 AACK/TA/TS/DBG/BG/BR sp11a/sp10 ARTRY/ TEA sp12/sp10 Data bus in normal mode sp13/sp10 Data bus in ECC and PARITY modes sp13a/sp10 Pipeline mode-- Data bus in ECC and PARITY modes sp14/sp10 DP pins sp14a/sp10 Pipeline mode--DP pins sp15/sp10 All other pins
1
Hold (ns) 83 MHz 100 MHz 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5
83 MHz 100 MHz 66 MHz 5 5 4 6 4 6 4 4 3.5 4 3.5 3.5 2.5 3.5 2.5 3.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5
6 6 5 8 -- 7 -- 5
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin.
Table 11 lists SIU output characteristics.
Table 11. AC Characteristics for SIU Outputs1
Spec_num (max/min) sp31/sp30 sp32/sp30 sp33a/sp30 sp33b/sp30 sp34/sp30 sp35/sp30 sp35a/sp30
1
Maximum Delay (ns) Characteristic 66 MHz PSDVAL/TEA/TA ADD/ADD_atr./BADDR/CI/GBL/WT Data bus2, 3 DP Memory controller All other signals2 AP signals/ALE2
2,3
Minimum Delay (ns) 83 MHz 100 MHz 0.5 0.52 0.52 1 0.52 0.52 0.5 0.5 0.52 0.52 1 0.52 0.52 0.5
83 MHz 100 MHz 66 MHz 6 6.5 6.5 7 5.5 5.5 7 5.5 5.5 5.5 6 5.5 5.5 7 0.5 0.52 0.52 1 0.52 0.52 0.5
7 8 6.5 8 6 6 7
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2 The signals in boldface have a minimum delay of 1 ns at 66.67/83.33/100 MHZ when communicating to SDRAM: LCL_D[0-31] OE/SDRAS/GP12 LSDCAS/GP13 A[0-31] LCL_DP[0-3] BADDR[27-31] SDCAS/GP13 MODCLK[1-3]/AP[1-3]/TC[0-2]/BNKSEL[0-2] CS[0-11] D[0-63] LWE[0-3]/LSDDQM[0-3]/LBS[0-3] LSDA10/GP10 SDA10/GP10 DP[0-7] LSDWE/GP11 PWE[0-7]/PSDDQM[0-7]/PBS[0-7] SDWE/GP11 L_A[14-31] LOE/LSDRAS/GP12 3 A minimum loading of 20 pF is required to meet 1 ns hold time for communicating to SDRAM.
NOTE Activating data pipelining (setting BRx[DR] in the memory controller) improves the AC timing. Also, sp33a can be used as the AC specification for DP signals.
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MPC8280 Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Electrical and Thermal Characteristics
Figure 8 shows the interaction of several bus signals.
CLKin sp11 AACK/ARTRY/TA/TS/TEA/ DBG/BG/BR input signals sp12 DATA bus normal mode input signal sp15 All other input signals sp31 PSDVAL/TEA/TA output signals sp32 ADD/ADD_atr/BADDR/CI/ GBL/WT output signals sp33a DATA bus output signals sp30 sp30 sp10 sp10 sp10
sp30
sp35
sp30
All other output signals
Figure 8. Bus Signals
Figure 9 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).
CLKin sp10 sp13 DATA bus, ECC, and PARITY mode input signals
sp10 sp14 DP mode input signal
sp33b/sp30 DP mode output signal
Figure 9. Parity Mode Diagram
Figure 10 shows signal behavior in MEMC mode.
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MPC8280 Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
CLKin
V_CLK
Memory controller signals
sp34/sp30
Figure 10. MEMC Mode Diagram
NOTE Generally, all MPC8280 bus and system output signals are driven from the rising edge of the input clock (CLKin). Memory controller signals, however, trigger on four points within a CLKin cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge, and T3 at the falling edge, of CLKin. However, the spacing of T2 and T4 depends on the PLL clock ratio selected, as shown in Table 12.
Table 12. Tick Spacing for Memory Controller Signals
Tick Spacing (T1 Occurs at the Rising Edge of CLKin) PLL Clock Ratio T2 1:2, 1:3, 1:4, 1:5, 1:6 1:2.5 1:3.5 1/4 CLKin 3/10 CLKin 4/14 CLKin T3 1/2 CLKin 1/2 CLKin 1/2 CLKin T4 3/4 CLKin 8/10 CLKin 11/14 CLKin
Figure 11 is a representation of the information in Table 12.
CLKin T1 T2 T3 T4 for 1:2, 1:3, 1:4, 1:5, 1:6
CLKin T1 T2 T3 T4
for 1:2.5
CLKin T1 T2 T3 T4
for 1:3.5
Figure 11. Internal Tick Spacing for Memory Controller Signals
NOTE The UPM machine outputs change on the internal tick determined by the memory controller programming; the AC specifications are relative to the internal tick. Note that SDRAM and GPCM machine outputs change on CLKin's rising edge.
MOTOROLA
MPC8280 Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
17
Clock Configuration Modes
1.3
Clock Configuration Modes
Table 13. MPC8280 Clocking Modes
Pins Clocking Mode Local bus PCI Host PCI Clock Frequency Range (MHZ) -- 50-66 25-50 PCI Agent 50-66 25-50 Reference Table 14 Table 15 Table 16 Table 17 Table 18
The MPC8280 has three clocking modes: local, PCI host, and PCI agent. The clocking mode is set according to three input pins--PCI_MODE, PCI_CFG[0], PCI_MODCK--as shown in Table 13.
PCI_MODE 1 0 0 0 0
1
PCI_CFG[0] PCI_MODCK1 -- 0 0 1 1 -- 0 1 0 1
Determines PCI clock frequency range. Refer to Section 1.3.2, "PCI Mode."
In each clocking mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven bits during the power-up reset--three hardware configuration pins (MODCK[1-3]) and four bits from hardware configuration word[28-31] (MODCK_H). Both the PLLs and the dividers are set according to the selected MPC8280 clock operation mode as described in the following sections.
1.3.1
Local Bus Mode
NOTE Clock configurations change only after POR is asserted.
Table 14 lists default and full configurations for the MPC8280 in local bus mode.
Note also that basic modes are shown in boldface type.
Table 14. Local Bus Clock Modes
Mode1 MODCK_H-MODCK[1-3] Bus Clock2,3 (MHz) low high CPM Multiplication Factor4 CPM Clock3 (MHz) low high CPU Multiplication Factor5 CPU Clock3 (MHz) low high
Default Modes (MODCK_H= 0000) 0000_000 0000_001 0000_010 0000_011 0000_100 0000_101 0000_110 0000_111 62.5 50.0 62.5 50.0 50.0 50.0 50.0 41.7 133.3 133.3 100.0 100.0 167.0 167.0 160.0 160.0 3 3 4 4 2 2 2.5 2.5 187.5 150.0 250.0 200.0 100.0 100.0 125.0 104.2 400.0 400.0 400.0 400.0 334.0 334.0 400.0 400.0 4 5 4 5 2.5 3 2.5 3 250.0 250.0 250.0 250.0 125.0 150.0 125.0 125.0 533.3 666.7 400.0 500.0 417.5 501.0 400.0 480.0
Full Configuration Modes
18
MPC8280 Hardware Specifications
MOTOROLA
Clock Configuration Modes Table 14. Local Bus Clock Modes (Continued)
Mode1 MODCK_H-MODCK[1-3] 0001_000 0001_001 0001_010 0001_011 0001_100 Bus Clock2,3 (MHz) low 62.5 50.0 50.0 high 167.0 167.0 167.0 CPM Multiplication Factor4 2 2 2 CPM Clock3 (MHz) low 125.0 100.0 100.0 high 334.0 334.0 334.0 CPU Multiplication Factor5 4 5 6 CPU Clock3 (MHz) low 250.0 250.0 300.0 high 668.0 835.0 1002.0
Reserved Reserved
0001_101 0001_110 1000_111 0001_111 0010_000 0010_001
62.5 50.0 45.5 41.7
133.3 133.3 133.3 133.3
3 3 3 3
187.5 150.0 136.4 125.0
400.0 400.0 400.0 400.0
4 5 5.5 6
250.0 250.0 250.0 250.0
533.3 666.7 733.3 800.0
Reserved Reserved
0010_010 0010_011 0010_100 0010_101 0010_110
62.5 50.0 41.7 35.7 31.3
100.0 100.0 100.0 100.0 100.0
4 4 4 4 4
250.0 200.0 166.7 142.9 125.0
400.0 400.0 400.0 400.0 400.0
4 5 6 7 8
250.0 250.0 250.0 250.0 250.0
400.0 500.0 600.0 700.0 800.0
0010_111 0011_000 0011_001 0011_010 0011_011 50.0 41.7 35.7 31.3 80.0 80.0 80.0 80.0 5 5 5 5
Reserved 250.0 208.3 178.6 156.3 400.0 400.0 400.0 400.0 5 6 7 8 250.0 250.0 250.0 250.0 400.0 480.0 560.0 640.0
0011_100 0011_101 0011_110 0011_111 0100_000 41.7 35.7 31.3 66.7 66.7 66.7 6 6 6
Reserved Reserved 250.0 214.3 187.5 400.0 400.0 400.0 6 7 8 250.0 250.0 250.0 400.0 466.7 533.3
0101_101 0101_110 0101_111
62.5 50.0 50.0
167.0 167.0 167.0
2 2 2
125.0 100.0 100.0
334.0 334.0 334.0
2 2.5 3
125.0 125.0 150.0
334.0 417.5 501.0
MOTOROLA
MPC8280 Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
19
Clock Configuration Modes Table 14. Local Bus Clock Modes (Continued)
Mode1 MODCK_H-MODCK[1-3] 0110_000 0110_001 0110_010 Bus Clock2,3 (MHz) low 71.4 62.5 55.6 high 167.0 167.0 167.0 CPM Multiplication Factor4 2 2 2 CPM Clock3 (MHz) low 142.9 125.0 111.1 high 334.0 334.0 334.0 CPU Multiplication Factor5 3.5 4 4.5 CPU Clock3 (MHz) low 250.0 250.0 250.0 high 584.5 668.0 751.5
0110_011 0110_100 0110_101 0110_110 0110_111 0111_000 50.0 41.7 71.4 62.5 55.6 160.0 160.0 160.0 160.0 160.0 2.5 2.5 2.5 2.5 2.5
Reserved 125.0 104.2 178.6 156.3 138.9 400.0 400.0 400.0 400.0 400.0 2.5 3 3.5 4 4.5 125.0 125.0 250.0 250.0 250.0 400.0 480.0 560.0 640.0 720.0
0111_001 0111_010 0111_011 0111_100 0111_101 0111_110 41.7 71.4 62.5 55.6 133.3 133.3 133.3 133.3 3 3 3 3
Reserved Reserved 125.0 214.3 187.5 166.7 400.0 400.0 400.0 400.0 3 3.5 4 4.5 125.0 250.0 250.0 250.0 400.0 466.7 533.3 600.0
0111_111 1000_000 1000_001 1000_010 1000_011 1000_100 1000_101 1000_110 71.4 62.5 55.6 50.0 45.5 114.3 114.3 114.3 114.3 114.3 3.5 3.5 3.5 3.5 3.5
Reserved Reserved Reserved 250.0 218.8 194.4 175.0 159.1 400.0 400.0 400.0 400.0 400.0 3.5 4 4.5 5 5.5 250.0 250.0 250.0 250.0 250.0 400.0 457.1 514.3 571.4 628.6
1100_000 1100_001 1100_010
50.0 40.0 33.3
167.0 160.0 133.3
2 2.5 3
100.0 100.0 100.0
334.0 400.0 400.0
Bypass Bypass Bypass
50.0 40.0 33.3
167.0 160.0 133.3
1101_000
1
Reserved
MODCK_H = hard reset configuration word [28-31]. Refer to Section 5.4 in the MPC8260 User's Manual; MODCK[1-3] = three hardware configuration pins.
20
MPC8280 Hardware Specifications
MOTOROLA
Clock Configuration Modes
2 3
60x and local bus frequency. Identical to CLKIN. `High' and `low' indicate frequency limits for a given configuration. 4 CPM multiplication factor = CPM clock/bus clock 5 CPU multiplication factor = Core PLL multiplication factor
1.3.2
PCI Mode
The following tables show the possible clock configurations for the MPC8280 in both PCI host and PCI agent modes. In addition, note the following: NOTE In PCI mode only, PCI_MODCK comes from the LGPL5 pin and MODCK_H[0-3] comes from {LGPL0, LGPL1, LGPL2, LGPL3}. NOTE The minimum Tval = 2 when PCI_MODCK = 1 and minimum Tval = 1 when PCI_MODCK = 0; therefore, board designers should use clock configurations that fit this condition to achieve PCI-compliant AC timing.
1.3.2.1
PCI Host Mode
Table 15 and Table 16 show configurations for PCI host mode. Note that the range of the PCI clock frequency is determined by PCI_MODCK.
Table 15. Clock Configurations for PCI Host Mode (PCI_MODCK=0)1
Mode2 MODCK_HMODCK[1-3] Bus Clock3,4 (MHz) low high CPM Multiplication Factor5 CPM Clock4 (MHz) low high CPU Multiplication Factor6 CPU Clock4 (MHz) low high PCI Division Factor PCI Clock (MHz) low high
Default Modes (MODCK_H=0000) 0000_000 0000_001 0000_010 0000_011 0000_100 0000_101 0000_110 0000_111 62.5 66.7 3 50.0 50.0 60.0 71.4 62.5 50.0 66.7 66.7 80.0 80.0 80.0 66.7 2 2 2.5 2.5 2.5 3 100.0 133.3 100.0 133.3 150.0 200.0 178.6 200.0 156.3 200.0 150.0 200.0 2.5 3 3 3.5 4 3 125.0 166.7 150.0 200.0 180.0 240.0 250.0 280.0 250.0 320.0 150.0 200.0 2 2 3 3 3 3 50.0 66.7 50.0 66.7 50.0 66.7 59.5 66.7 52.1 66.7 50.0 66.7
PCI host mode (PCI_MODCK=1) only (refer to Table 16) 187.5 200.0 4 250.0 266.6 3 62.5 66.7
Full Configuration Modes 0001_000 0001_001 0001_010 0001_011 50.0 50.0 50.0 50.0 66.7 66.7 66.7 66.7 3 3 3 3 150.0 200.0 150.0 200.0 150.0 200.0 150.0 200.0 5 6 7 8 250.0 333.3 300.0 400.0 350.0 466.6 400.0 533.3 3 3 3 3 50.0 66.7 50.0 66.7 50.0 66.7 50.0 66.7
MOTOROLA
MPC8280 Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
21
Clock Configuration Modes Table 15. Clock Configurations for PCI Host Mode (PCI_MODCK=0)1 (Continued)
Mode2 MODCK_HMODCK[1-3] 0010_000 0010_001 0010_010 0010_011 Bus Clock3,4 (MHz) low 50.0 50.0 50.0 50.0 high 66.7 66.7 66.7 66.7 CPM Multiplication Factor5 4 4 4 4 CPM Clock4 (MHz) low high CPU Multiplication Factor6 5 6 7 8 CPU Clock4 (MHz) low high PCI Division Factor 4 4 4 4 PCI Clock (MHz) low high 50.0 66.7 50.0 66.7 50.0 66.7 50.0 66.7
200.0 266.6 200.0 266.6 200.0 266.6 200.0 266.6
250.0 333.3 300.0 400.0 350.0 466.6 400.0 533.3
0010_100 0010_101 0010_110
75.0 100.0 75.0 100.0 75.0 100.0
4 4 4
300.0 400.0 300.0 400.0 300.0 400.0
5 5.5 6
375.0 500.0 412.5 549.9 450.0 599.9
6 6 6
50.0 66.7 50.0 66.7 50.0 66.7
0011_000 0011_001 0011_010 0011_011
50.0 50.0 50.0 50.0
66.7 66.7 66.7 66.7
5 5 5 5
250.0 333.3 250.0 333.3 250.0 333.3 250.0 333.3
5 6 7 8
250.0 333.3 300.0 400.0 350.0 466.6 400.0 533.3
5 5 5 5
50.0 66.7 50.0 66.7 50.0 66.7 50.0 66.7
0100_000 0100_001 0100_010 0100_011 50.0 50.0 50.0 66.7 66.7 66.7 6 6 6 300.0 400.0 300.0 400.0 300.0 400.0
Reserved 6 7 8 300.0 400.0 350.0 466.6 400.0 533.3 6 6 6 50.0 66.7 50.0 66.7 50.0 66.7
0101_000 0101_001 0101_010 0101_011 0101_100
50.0 50.0
66.7 66.7
2 2
100.0 133.3 100.0 133.3
2.5 3
125.0 166.7 150.0 200.0
2 2
50.0 66.7 50.0 66.7
PCI host mode (PCI_MODCK=1) only (refer to Table 16) 62.5 55.6 66.7 66.7 2 2 125.0 133.3 111.1 133.3 4 4.5 250.0 266.6 250.0 300.0 2 2 62.5 66.7 55.6 66.7
0110_000 0110_001 0110_010 0110_011 0110_100 0110_101 0110_110
60.0 60.0 71.4 62.5 60.0 60.0 60.0
80.0 80.0 80.0 80.0 80.0 80.0 80.0
2.5 2.5 2.5 2.5 2.5 2.5 2.5
150.0 200.0 150.0 200.0 178.6 200.0 156.3 200.0 150.0 200.0 150.0 200.0 150.0 200.0
2.5 3 3.5 4 4.5 5 6
150.0 200.0 180.0 240.0 250.0 280.0 250.0 320.0 270.0 360.0 300.0 400.0 360.0 480.0
3 3 3 3 3 3 3
50.0 66.7 50.0 66.7 59.5 66.7 52.1 66.7 50.0 66.7 50.0 66.7 50.0 66.7
22
MPC8280 Hardware Specifications
MOTOROLA
Clock Configuration Modes Table 15. Clock Configurations for PCI Host Mode (PCI_MODCK=0)1 (Continued)
Mode2 MODCK_HMODCK[1-3] 0111_000 0111_001 0111_010 0111_011 0111_100 62.5 55.6 66.7 66.7 3 3 50.0 66.7 3 150.0 200.0 Bus Clock3,4 (MHz) low high CPM Multiplication Factor5 CPM Clock4 (MHz) low high CPU Multiplication Factor6 Reserved 3 150.0 200.0 3 50.0 66.7 CPU Clock4 (MHz) low high PCI Division Factor PCI Clock (MHz) low high
PCI host mode (PCI_MODCK=1) only (refer to Table 16) 187.5 200.0 166.7 200.0 4 4.5 250.0 266.6 250.0 300.0 3 3 62.5 66.7 55.6 66.7
1000_000 1000_001 1000_010 1000_011 1000_100 1000_101 1000_110 66.7 71.4 66.7 66.7 66.7 66.7 88.9 88.9 88.9 88.9 88.9 88.9 3 3 3 3 3 3 200.0 266.6 214.3 266.6 200.0 266.6 200.0 266.6 200.0 266.6 200.0 266.6
Reserved 3 3.5 4 4.5 6 6.5 200.0 266.6 250.0 311.1 266.7 355.5 300.0 400.0 400.0 533.3 433.3 577.7 4 4 4 4 4 4 50.0 66.7 53.6 66.7 50.0 66.7 50.0 66.7 50.0 66.7 50.0 66.7
1001_000 1001_001 1001_010 1001_011 1001_100
57.1 57.1 71.4 62.5 57.1
76.2 76.2 76.2 76.2 76.2
3.5 3.5 3.5 3.5 3.5
200.0 266.6 200.0 266.6 250.0 266.6 218.8 266.6 200.0 266.6
2.5 3 3.5 4 4.5
142.9 190.5 171.4 228.5 250.0 266.6 250.0 304.7 257.1 342.8
4 4 4 4 4
50.0 66.7 50.0 66.7 62.5 66.7 54.7 66.7 50.0 66.7
1001_101 1001_110 1001_111
85.7 114.3 85.7 114.3 85.7 114.3
3.5 3.5 3.5
300.0 400.0 300.0 400.0 300.0 400.0
5 5.5 6
428.6 571.4 471.4 628.5 514.3 685.6
6 6 6
50.0 66.7 50.0 66.7 50.0 66.7
1010_000 1010_001 1010_010 1010_011 1010_100
75.0 100.0 75.0 100.0 75.0 100.0 75.0 100.0 75.0 100.0
2 2 2 2 2
150.0 200.0 150.0 200.0 150.0 200.0 150.0 200.0 150.0 200.0
2 2.5 3 3.5 4
150.0 200.0 187.5 250.0 225.0 300.0 262.5 350.0 300.0 400.0
3 3 3 3 3
50.0 66.7 50.0 66.7 50.0 66.7 50.0 66.7 50.0 66.7
1011_000 1011_001 1011_010 80.0 106.7 80.0 106.7 2.5 2.5 200.0 266.6 200.0 266.6
Reserved 2.5 3 200.0 266.6 240.0 320.0 4 4 50.0 66.7 50.0 66.7
MOTOROLA
MPC8280 Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
23
Clock Configuration Modes Table 15. Clock Configurations for PCI Host Mode (PCI_MODCK=0)1 (Continued)
Mode2 MODCK_HMODCK[1-3] 1011_011 1011_100 1011_101 Bus Clock3,4 (MHz) low high CPM Multiplication Factor5 2.5 2.5 2.5 CPM Clock4 (MHz) low high CPU Multiplication Factor6 3.5 4 4.5 CPU Clock4 (MHz) low high PCI Division Factor 4 4 4 PCI Clock (MHz) low high 50.0 66.7 50.0 66.7 50.0 66.7
80.0 106.7 80.0 106.7 80.0 106.7
200.0 266.6 200.0 266.6 200.0 266.6
280.0 373.3 320.0 426.6 360.0 480.0
1101_000 1101_001 1101_010 1101_011 1101_100
100.0 133.3 100.0 133.3 100.0 133.3 100.0 133.3 100.0 133.3
2.5 2.5 2.5 2.5 2.5
250.0 333.3 250.0 333.3 250.0 333.3 250.0 333.3 250.0 333.3
3 3.5 4 4.5 5
300.0 400.0 350.0 466.6 400.0 533.3 450.0 599.9 500.0 666.6
5 5 5 5 5
50.0 66.7 50.0 66.7 50.0 66.7 50.0 66.7 50.0 66.7
1101_101 1101_110
125.0 166.7 125.0 166.7
2 2
250.0 333.3 250.0 333.3
3 4
375.0 500.0 500.0 666.6
5 5
50.0 66.7 50.0 66.7
1110_000 1110_001 1110_010 1110_011 1110_100
100.0 133.3 100.0 133.3 100.0 133.3 100.0 133.3 100.0 133.3
3 3 3 3 3
300.0 400.0 300.0 400.0 300.0 400.0 300.0 400.0 300.0 400.0
3.5 4 4.5 5 5.5
350.0 466.6 400.0 533.3 450.0 599.9 500.0 666.6 550.0 733.3
6 6 6 6 6
50.0 66.7 50.0 66.7 50.0 66.7 50.0 66.7 50.0 66.7
1100_000 1100_001 1100_010
1 2 3 4 5 6
50.0 60.0 50.0
66.7 80.0 66.7
2 2.5 3
100.0 133.3 150.0 200.0 150.0 200.0
Bypass Bypass Bypass
50.0 60.0 50.0
66.7 80.0 66.7
2 3 3
50.0 66.7 50.0 66.7 50.0 66.7
As shown in Table 13, PCI_MODCK determines the PCI clock frequency range. Refer to Table 16 for lower range configurations. MODCK_H = hard reset configuration word [28-31]. Refer to Section 5.4 in the MPC8260 User's Manual; MODCK[1-3] = three hardware configuration pins. 60x and local bus frequency. Identical to CLKIN. `High' and `low' indicate frequency limits for a given configuration. CPM multiplication factor = CPM clock/bus clock CPU multiplication factor = Core PLL multiplication factor
24
MPC8280 Hardware Specifications
MOTOROLA
Clock Configuration Modes Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=1)1
Mode2 MODCK_HMODCK[1-3] Bus Clock3,4 (MHz) low high CPM Multiplication Factor5 CPM Clock4 (MHz) low high CPU Multiplication Factor6 CPU Clock4 (MHz) low high PCI Division Factor PCI Clock (MHz) low high
Default Modes (MODCK_H=0000) 0000_000 0000_001 0000_010 0000_011 0000_100 0000_101 0000_110 0000_111 50.0 50.0 60.0 71.4 62.5 50.0 71.4 62.5 100.0 100.0 120.0 120.0 120.0 100.0 100.0 100.0 2 2 2.5 2.5 2.5 3 3 3 100.0 200.0 100.0 200.0 150.0 300.0 178.6 300.0 156.3 300.0 150.0 300.0 214.3 300.0 187.5 300.0 2.5 3 3 3.5 4 3 3.5 4 125.0 250.0 150.0 300.0 180.0 360.0 250.0 420.0 250.0 480.0 150.0 300.0 250.0 350.0 250.0 400.0 4 4 6 6 6 6 6 6 25.0 50.0 25.0 50.0 25.0 50.0 29.8 50.0 26.0 50.0 25.0 50.0 35.7 50.0 31.3 50.0
Full Configuration Modes 0001_000 0001_001 0001_010 0001_011 50.0 50.0 50.0 50.0 100.0 100.0 100.0 100.0 3 3 3 3 150.0 300.0 150.0 300.0 150.0 300.0 150.0 300.0 5 6 7 8 250.0 500.0 300.0 600.0 350.0 700.0 400.0 800.0 6 6 6 6 25.0 50.0 25.0 50.0 25.0 50.0 25.0 50.0
0010_000 0010_001 0010_010 0010_011
50.0 50.0 50.0 50.0
100.0 100.0 100.0 100.0
4 4 4 4
200.0 400.0 200.0 400.0 200.0 400.0 200.0 400.0
5 6 7 8
250.0 500.0 300.0 600.0 350.0 700.0 400.0 800.0
8 8 8 8
25.0 50.0 25.0 50.0 25.0 50.0 25.0 50.0
0010_100 0010_101 0010_110
50.0 45.5 41.7
75.0 75.0 75.0
4 4 4
200.0 300.0 181.8 300.0 166.7 300.0
5 5.5 6
250.0 375.0 250.0 412.5 250.0 450.0
6 6 6
33.3 50.0 30.3 50.0 27.8 50.0
0011_000 0011_001 0011_010 0011_011
50.0 41.7 35.7 31.3
50.0 50.0 50.0 50.0
5 5 5 5
250.0 250.0 208.3 250.0 178.6 250.0 156.3 250.0
5 6 7 8
250.0 250.0 250.0 300.0 250.0 350.0 250.0 400.0
5 5 5 5
50.0 50.0 41.7 50.0 35.7 50.0 31.3 50.0
0100_000 0100_001 0100_010 0100_011 41.7 35.7 31.3 50.0 50.0 50.0 6 6 6 250.0 300.0 214.3 300.0 187.5 300.0
Reserved 6 7 8 250.0 300.0 250.0 350.0 250.0 400.0 6 6 6 41.7 50.0 35.7 50.0 31.3 50.0
MOTOROLA
MPC8280 Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
25
Clock Configuration Modes Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=1)1 (Continued)
Mode2 MODCK_HMODCK[1-3] Bus Clock3,4 (MHz) low high CPM Multiplication Factor5 CPM Clock4 (MHz) low high CPU Multiplication Factor6 CPU Clock4 (MHz) low high PCI Division Factor PCI Clock (MHz) low high
0101_000 0101_001 0101_010 0101_011 0101_100
50.0 50.0 71.4 62.5 55.6
100.0 100.0 100.0 100.0 100.0
2 2 2 2 2
100.0 200.0 100.0 200.0 142.9 200.0 125.0 200.0 111.1 200.0
2.5 3 3.5 4 4.5
125.0 250.0 150.0 300.0 250.0 350.0 250.0 400.0 250.0 450.0
4 4 4 4 4
25.0 50.0 25.0 50.0 35.7 50.0 31.3 50.0 27.8 50.0
0110_000 0110_001 0110_010 0110_011 0110_100 0110_101 0110_110
60.0 60.0 71.4 62.5 60.0 60.0 60.0
120.0 120.0 120.0 120.0 120.0 120.0 120.0
2.5 2.5 2.5 2.5 2.5 2.5 2.5
150.0 300.0 150.0 300.0 178.6 300.0 156.3 300.0 150.0 300.0 150.0 300.0 150.0 300.0
2.5 3 3.5 4 4.5 5 6
150.0 300.0 180.0 360.0 250.0 420.0 250.0 480.0 270.0 540.0 300.0 600.0 360.0 720.0
6 6 6 6 6 6 6
25.0 50.0 25.0 50.0 29.8 50.0 26.0 50.0 25.0 50.0 25.0 50.0 25.0 50.0
0111_000 0111_001 0111_010 0111_011 0111_100 50.0 71.4 62.5 55.6 100.0 100.0 100.0 100.0 3 3 3 3 150.0 300.0 214.3 300.0 187.5 300.0 166.7 300.0
Reserved 3 3.5 4 4.5 150.0 300.0 250.0 350.0 250.0 400.0 250.0 450.0 6 6 6 6 25.0 50.0 35.7 50.0 31.3 50.0 27.8 50.0
1000_000 1000_001 1000_010 1000_011 1000_100 1000_101 1000_110 66.7 71.4 66.7 66.7 66.7 66.7 133.3 133.3 133.3 133.3 133.3 133.3 3 3 3 3 3 3 200.0 400.0 214.3 400.0 200.0 400.0 200.0 400.0 200.0 400.0 200.0 400.0
Reserved 3 3.5 4 4.5 6 6.5 200.0 400.0 250.0 466.7 266.7 533.3 300.0 600.0 400.0 800.0 433.3 866.7 8 8 8 8 8 8 25.0 50.0 26.8 50.0 25.0 50.0 25.0 50.0 25.0 50.0 25.0 50.0
1001_000 1001_001 1001_010 1001_011 71.4 62.5 114.3 114.3 3.5 3.5 250.0 400.0 218.8 400.0
Reserved Reserved 3.5 4 250.0 400.0 250.0 457.1 8 8 31.3 50.0 27.3 50.0
26
MPC8280 Hardware Specifications
MOTOROLA
Clock Configuration Modes Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=1)1 (Continued)
Mode2 MODCK_HMODCK[1-3] 1001_100 Bus Clock3,4 (MHz) low 57.1 high 114.3 CPM Multiplication Factor5 3.5 CPM Clock4 (MHz) low high CPU Multiplication Factor6 4.5 CPU Clock4 (MHz) low high PCI Division Factor 8 PCI Clock (MHz) low high 25.0 50.0
200.0 400.0
257.1 514.3
1001_101 1001_110 1001_111
50.0 45.5 42.9
85.7 85.7 85.7
3.5 3.5 3.5
175.0 300.0 159.1 300.0 150.0 300.0
5 5.5 6
250.0 428.6 250.0 471.4 257.1 514.3
6 6 6
29.2 50.0 26.5 50.0 25.0 50.0
1010_000 1010_001 1010_010 1010_011 1010_100
75.0 75.0 75.0 75.0 75.0
150.0 150.0 150.0 150.0 150.0
2 2 2 2 2
150.0 300.0 150.0 300.0 150.0 300.0 150.0 300.0 150.0 300.0
2 2.5 3 3.5 4
150.0 300.0 187.5 375.0 225.0 450.0 262.5 525.0 300.0 600.0
6 6 6 6 6
25.0 50.0 25.0 50.0 25.0 50.0 25.0 50.0 25.0 50.0
1011_000 1011_001 1011_010 1011_011 1011_100 1011_101 80.0 80.0 80.0 80.0 80.0 160.0 160.0 160.0 160.0 160.0 2.5 2.5 2.5 2.5 2.5 200.0 400.0 200.0 400.0 200.0 400.0 200.0 400.0 200.0 400.0
Reserved 2.5 3 3.5 4 4.5 200.0 400.0 240.0 480.0 280.0 560.0 320.0 640.0 360.0 720.0 8 8 8 8 8 25.0 50.0 25.0 50.0 25.0 50.0 25.0 50.0 25.0 50.0
1101_000 1101_001 1101_010 1101_011 1101_100
50.0 71.4 62.5 55.6 50.0
100.0 100.0 100.0 100.0 100.0
2.5 2.5 2.5 2.5 2.5
125.0 250.0 178.6 250.0 156.3 250.0 138.9 250.0 125.0 250.0
3 3.5 4 4.5 5
150.0 300.0 250.0 350.0 250.0 400.0 250.0 450.0 250.0 500.0
5 5 5 5 5
25.0 50.0 35.7 50.0 31.3 50.0 27.8 50.0 25.0 50.0
1101_101 1101_110
62.5 62.5
125.0 125.0
2 2
125.0 250.0 125.0 250.0
3 4
187.5 375.0 250.0 500.0
5 5
25.0 50.0 25.0 50.0
1110_000 1110_001 1110_010 1110_011 1110_100
71.4 62.5 55.6 50.0 50.0
100.0 100.0 100.0 100.0 100.0
3 3 3 3 3
214.3 300.0 187.5 300.0 166.7 300.0 150.0 300.0 150.0 300.0
3.5 4 4.5 5 5.5
250.0 350.0 250.0 400.0 250.0 450.0 250.0 500.0 275.0 550.0
6 6 6 6 6
35.7 50.0 31.3 50.0 27.8 50.0 25.0 50.0 25.0 50.0
MOTOROLA
MPC8280 Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
27
Clock Configuration Modes Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=1)1 (Continued)
Mode2 MODCK_HMODCK[1-3] Bus Clock3,4 (MHz) low high CPM Multiplication Factor5 CPM Clock4 (MHz) low high CPU Multiplication Factor6 CPU Clock4 (MHz) low high PCI Division Factor PCI Clock (MHz) low high
1100_000 1100_001 1100_010
1 2 3 4 5 6
50.0 60.0 50.0
100.0 120.0 100.0
2 2.5 3
100.0 200.0 150.0 300.0 150.0 300.0
Bypass Bypass Bypass
50.0 100.0 60.0 120.0 50.0 100.0
4 6 6
25.0 50.0 25.0 50.0 25.0 50.0
As shown in Table 13, PCI_MODCK determines the PCI clock frequency range. Refer to Table 15 for higher range configurations. MODCK_H = hard reset configuration word [28-31]. Refer to Section 5.4 in the MPC8260 User's Manual; MODCK[1-3] = three hardware configuration pins. 60x and local bus frequency. Identical to CLKIN. `High' and `low' indicate frequency limits for a given configuration. CPM multiplication factor = CPM clock/bus clock CPU multiplication factor = Core PLL multiplication factor
1.3.2.2
PCI Agent Mode
Table 17 and Table 18 show configurations for PCI agent mode. Note that the range of the PCI clock frequency is determined by PCI_MODCK.
Table 17. Clock Configurations for PCI Agent Mode (PCI_MODCK=0)1
Mode2 MODCK_HMODCK[1-3] PCI Clock3 (MHz) low high CPM Multiplication Factor4 CPM Clock3 (MHz) low high CPU Multiplication Factor5 CPU Clock3 (MHz) low high Bus Division Factor Bus Clock3,6 (MHz) low high
Default Modes (MODCK_H=0000 0000_000 0000_001 0000_010 0000_011 0000_100 0000_101 0000_110 0000_111 50.0 66.7 50.0 66.7 50.0 66.7 62.5 66.7 50.0 66.7 59.5 66.7 53.6 66.7 50.0 66.7 2 2 3 3 3 3 4 4 100.0 133.3 100.0 133.3 150.0 200.0 187.5 200.0 150.0 200.0 178.6 200.0 214.3 266.6 200.0 266.6 2.5 3 3 4 3 3.5 3.5 3 125.0 166.7 150.0 200.0 150.0 200.0 250.0 266.6 180.0 240.0 250.0 280.0 250.0 311.1 240.0 320.0 2 2 3 3 2.5 2.5 3 2.5 50.0 50.0 50.0 62.5 60.0 71.4 71.4 66.7 66.7 66.7 66.7 80.0 80.0 88.9
80.0 106.7
Full Configuration Modes 0001_001 0001_010 0001_011 0001_100 62.5 66.7 2 125.0 133.3 Reserved Reserved Reserved 8 250.0 266.6 4 31.3 33.3
28
MPC8280 Hardware Specifications
MOTOROLA
Clock Configuration Modes Table 17. Clock Configurations for PCI Agent Mode (PCI_MODCK=0)1 (Continued)
Mode2 MODCK_HMODCK[1-3] PCI Clock3 (MHz) low high CPM Multiplication Factor4 CPM Clock3 (MHz) low high CPU Multiplication Factor5 CPU Clock3 (MHz) low high Bus Division Factor Bus Clock3,6 (MHz) low high
0010_001 0010_010 0010_011 0010_100
50.0 66.7 59.5 66.7 52.1 66.7 50.0 66.7
3 3 3 3
150.0 200.0 178.6 200.0 156.3 200.0 150.0 200.0
3 3.5 4 4.5
180.0 240.0 250.0 280.0 250.0 320.0 270.0 360.0
2.5 2.5 2.5 2.5
60.0 71.4 62.5 60.0
80.0 80.0 80.0 80.0
0011_000 0011_001 0011_010 0011_011 0011_100
Reserved Reserved Reserved Reserved Reserved
0100_000 0100_001 0100_010 0100_011 0100_100 62.5 66.7 55.6 66.7 3 3 187.5 200.0 166.7 200.0 50.0 66.7 3 150.0 200.0
Reserved 3 Reserved 4 4.5 250.0 266.6 250.0 300.0 3 3 62.5 55.6 66.7 66.7 150.0 200.0 3 50.0 66.7
0101_000 0101_001 0101_010 0101_011 0101_100 0101_101 0101_110
50.0 66.7 50.0 66.7 50.0 66.7 50.0 66.7 50.0 66.7 50.0 66.7 50.0 66.7
5 5 5 5 5 5 5
250.0 333.3 250.0 333.3 250.0 333.3 250.0 333.3 250.0 333.3 250.0 333.3 250.0 333.3
2.5 3 3.5 4 4.5 5 5.5
250.0 333.3 300.0 400.0 350.0 466.6 400.0 533.3 450.0 599.9 500.0 666.6 550.0 733.3
2.5 2.5 2.5 2.5 2.5 2.5 2.5
100.0 133.3 100.0 133.3 100.0 133.3 100.0 133.3 100.0 133.3 100.0 133.3 100.0 133.3
0110_000 0110_001 0110_010 0110_011 0110_100 50.0 66.7 53.6 66.7 50.0 66.7 50.0 66.7 4 4 4 4 200.0 266.6 214.3 266.6 200.0 266.6 200.0 266.6
Reserved 3 3.5 4 4.5 200.0 266.6 250.0 311.1 266.7 355.5 300.0 400.0 3 3 3 3 66.7 71.4 66.7 66.7 88.9 88.9 88.9 88.9
0111_000
50.0 66.7
3
150.0 200.0
2
150.0 200.0
2
75.0 100.0
MOTOROLA
MPC8280 Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
29
Clock Configuration Modes Table 17. Clock Configurations for PCI Agent Mode (PCI_MODCK=0)1 (Continued)
Mode2 MODCK_HMODCK[1-3] 0111_001 0111_010 0111_011 PCI Clock3 (MHz) low high 50.0 66.7 50.0 66.7 50.0 66.7 CPM Multiplication Factor4 3 3 3 CPM Clock3 (MHz) low high CPU Multiplication Factor5 2.5 3 3.5 CPU Clock3 (MHz) low high Bus Division Factor 2 2 2 Bus Clock3,6 (MHz) low high
150.0 200.0 150.0 200.0 150.0 200.0
187.5 250.0 225.0 300.0 262.5 350.0
75.0 100.0 75.0 100.0 75.0 100.0
1000_000 1000_001 1000_010 1000_011 1000_100 1000_101 50.0 66.7 50.0 66.7 59.5 66.7 52.1 66.7 50.0 66.7 3 3 3 3 3 150.0 200.0 150.0 200.0 178.6 200.0 156.3 200.0 150.0 200.0
Reserved 2.5 3 3.5 4 4.5 150.0 200.0 180.0 240.0 250.0 280.0 250.0 320.0 270.0 360.0 2.5 2.5 2.5 2.5 2.5 60.0 60.0 71.4 62.5 60.0 80.0 80.0 80.0 80.0 80.0
1001_000 1001_001 1001_010 1001_011 1001_100 62.5 66.7 55.6 66.7 4 4 250.0 266.6 222.2 266.6
Reserved Reserved Reserved 4 4.5 250.0 266.6 250.0 300.0 4 4 62.5 55.6 66.7 66.7
1010_000 1010_001 1010_010 1010_011 1010_100 50.0 66.7 53.6 66.7 50.0 66.7 50.0 66.7 4 4 4 4 200.0 266.6 214.3 266.6 200.0 266.6 200.0 266.6
Reserved 3 3.5 4 4.5 200.0 266.6 250.0 311.1 266.7 355.5 300.0 400.0 3 3 3 3 66.7 71.4 66.7 66.7 88.9 88.9 88.9 88.9
1011_000 1011_001 1011_010 1011_011 1011_100 50.0 66.7 50.0 66.7 50.0 66.7 50.0 66.7 4 4 4 4 200.0 266.6 200.0 266.6 200.0 266.6 200.0 266.6
Reserved 2.5 3 3.5 4 200.0 266.6 240.0 320.0 280.0 373.3 320.0 426.6 2.5 2.5 2.5 2.5 80.0 106.7 80.0 106.7 80.0 106.7 80.0 106.7
1100_101 1100_110 1100_111 1101_000
50.0 66.7 50.0 66.7 50.0 66.7 50.0 66.7
6 6 6 6
300.0 400.0 300.0 400.0 300.0 400.0 300.0 400.0
4 4.5 5 5.5
400.0 533.3 450.0 599.9 500.0 666.6 550.0 733.3
3 3 3 3
100.0 133.3 100.0 133.3 100.0 133.3 100.0 133.3
30
MPC8280 Hardware Specifications
MOTOROLA
Clock Configuration Modes Table 17. Clock Configurations for PCI Agent Mode (PCI_MODCK=0)1 (Continued)
Mode2 MODCK_HMODCK[1-3] PCI Clock3 (MHz) low high CPM Multiplication Factor4 CPM Clock3 (MHz) low high CPU Multiplication Factor5 CPU Clock3 (MHz) low high Bus Division Factor Bus Clock3,6 (MHz) low high
1101_001 1101_010 1101_011 1101_100
50.0 66.7 50.0 66.7 50.0 66.7 50.0 66.7
6 6 6 6
300.0 400.0 300.0 400.0 300.0 400.0 300.0 400.0
3.5 4 4.5 5
420.0 559.9 480.0 639.9 540.0 719.9 600.0 799.9
2.5 2.5 2.5 2.5
120.0 160.0 120.0 160.0 120.0 160.0 120.0 160.0
1110_000 1110_001 1110_010 1110_011
50.0 66.7 50.0 66.7 50.0 66.7 50.0 66.7
5 5 5 5
250.0 333.3 250.0 333.3 250.0 333.3 250.0 333.3
2.5 3 3.5 4
312.5 416.6 375.0 500.0 437.5 583.3 500.0 666.6
2 2 2 2
125.0 166.7 125.0 166.7 125.0 166.7 125.0 166.7
1110_100 1110_101 1110_110 1110_111
50.0 66.7 50.0 66.7 50.0 66.7 50.0 66.7
5 5 5 5
250.0 333.3 250.0 333.3 250.0 333.3 250.0 333.3
4 4.5 5 5.5
333.3 444.4 375.0 500.0 416.7 555.5 458.3 611.1
3 3 3 3
83.3 111.1 83.3 111.1 83.3 111.1 83.3 111.1
1100_000 1100_001 1100_010
1 2 3 4 5 6
50.0 66.7 50.0 66.7 50.0 66.7
2 3 3
100.0 133.3 150.0 200.0 150.0 200.0
Bypass Bypass Bypass
50.0 60.0 50.0
66.7 80.0 66.7
2 2.5 3
50.0 60.0 50.0
66.7 80.0 66.7
As shown in Table 13, PCI_MODCK determines the PCI clock frequency range. Refer to Table 18 for lower range configurations. MODCK_H = hard reset configuration word [28-31]. Refer to Section 5.4 in the MPC8260 User's Manual; MODCK[1-3] = three hardware configuration pins. `High' and `low' indicate frequency limits for a given configuration. CPM multiplication factor = CPM clock/bus clock CPU multiplication factor = Core PLL multiplication factor 60x and local bus frequency. Identical to CLKIN.
MOTOROLA
MPC8280 Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
31
Clock Configuration Modes Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=1)1
Mode2 MODCK_HMODCK[1-3] PCI Clock3 (MHz) low high CPM Multiplication Factor4 CPM Clock3 (MHz) low high CPU Multiplication Factor5 CPU Clock3 (MHz) low high Bus Division Factor Bus Clock3,6 (MHz) low high
Default Modes (MODCK_H=0000) 0000_000 0000_001 0000_010 0000_011 0000_100 0000_101 0000_110 0000_111 25.0 25.0 25.0 31.3 25.0 29.8 26.8 25.0 50.0 50.0 50.0 50.0 50.0 50.0 50.0 50.0 4 4 6 6 6 6 8 8 100.0 200.0 100.0 200.0 150.0 300.0 187.5 300.0 150.0 300.0 178.6 300.0 214.3 400.0 200.0 400.0 2.5 3 3 4 3 3.5 3.5 3 125.0 250.0 150.0 300.0 150.0 300.0 250.0 400.0 180.0 360.0 250.0 420.0 250.0 466.7 240.0 480.0 2 2 3 3 2.5 2.5 3 2.5 50.0 100.0 50.0 100.0 50.0 100.0 62.5 100.0 60.0 120.0 71.4 120.0 71.4 133.3 80.0 160.0
Full Configuration Modes 0001_001 0001_010 0001_011 0001_100 50.0 41.7 35.7 31.3 50.0 50.0 50.0 50.0 4 4 4 4 200.0 200.0 166.7 200.0 142.9 200.0 125.0 200.0 5 6 7 8 250.0 250.0 250.0 300.0 250.0 350.0 250.0 400.0 4 4 4 4 50.0 41.7 35.7 31.3 50.0 50.0 50.0 50.0
0010_001 0010_010 0010_011 0010_100
25.0 29.8 26.0 25.0
50.0 50.0 50.0 50.0
6 6 6 6
150.0 300.0 178.6 300.0 156.3 300.0 150.0 300.0
3 3.5 4 4.5
180.0 360.0 250.0 420.0 250.0 480.0 270.0 540.0
2.5 2.5 2.5 2.5
60.0 120.0 71.4 120.0 62.5 120.0 60.0 120.0
0011_000 0011_001 0011_010 0011_011 0011_100 46.9 41.7 50.0 50.0 4 4 187.5 200.0 166.7 200.0 31.3 50.0 4 125.0 200.0
Reserved 2.5 Reserved 4 4.5 250.0 266.7 250.0 300.0 3 3 62.5 55.6 66.7 66.7 125.0 200.0 3 41.7 66.7
0100_000 0100_001 0100_010 0100_011 0100_100 25.0 35.7 31.3 27.8 50.0 50.0 50.0 50.0 6 6 6 6 150.0 300.0 214.3 300.0 187.5 300.0 166.7 300.0
Reserved 3 3.5 4 4.5 150.0 300.0 250.0 350.0 250.0 400.0 250.0 450.0 3 3 3 3 50.0 100.0 71.4 100.0 62.5 100.0 55.6 100.0
32
MPC8280 Hardware Specifications
MOTOROLA
Clock Configuration Modes Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=1)1 (Continued)
Mode2 MODCK_HMODCK[1-3] 0101_000 0101_001 0101_010 0101_011 0101_100 0101_101 0101_110 PCI Clock3 (MHz) low 25.0 25.0 35.7 31.3 27.8 25.0 25.0 high 50.0 50.0 50.0 50.0 50.0 50.0 50.0 CPM Multiplication Factor4 5 5 5 5 5 5 5 CPM Clock3 (MHz) low high CPU Multiplication Factor5 2.5 3 3.5 4 4.5 5 5.5 CPU Clock3 (MHz) low high Bus Division Factor 2.5 2.5 2.5 2.5 2.5 2.5 2.5 Bus Clock3,6 (MHz) low high
125.0 250.0 125.0 250.0 178.6 250.0 156.3 250.0 138.9 250.0 125.0 250.0 125.0 250.0
125.0 250.0 150.0 300.0 250.0 350.0 250.0 400.0 250.0 450.0 250.0 500.0 275.0 550.0
50.0 100.0 50.0 100.0 71.4 100.0 62.5 100.0 55.6 100.0 50.0 100.0 50.0 100.0
0110_000 0110_001 0110_010 0110_011 0110_100 25.0 26.8 25.0 25.0 50.0 50.0 50.0 50.0 8 8 8 8 200.0 400.0 214.3 400.0 200.0 400.0 200.0 400.0
Reserved 3 3.5 4 4.5 200.0 400.0 250.0 466.7 266.7 533.3 300.0 600.0 3 3 3 3 66.7 133.3 71.4 133.3 66.7 133.3 66.7 133.3
0111_000 0111_001 0111_010 0111_011
25.0 25.0 25.0 25.0
50.0 50.0 50.0 50.0
6 6 6 6
150.0 300.0 150.0 300.0 150.0 300.0 150.0 300.0
2 2.5 3 3.5
150.0 300.0 187.5 375.0 225.0 450.0 262.5 525.0
2 2 2 2
75.0 150.0 75.0 150.0 75.0 150.0 75.0 150.0
1000_000 1000_001 1000_010 1000_011 1000_100 1000_101 25.0 25.0 29.8 26.0 25.0 50.0 50.0 50.0 50.0 50.0 6 6 6 6 6 150.0 300.0 150.0 300.0 178.6 300.0 156.3 300.0 150.0 300.0
Reserved 2.5 3 3.5 4 4.5 150.0 300.0 180.0 360.0 250.0 420.0 250.0 480.0 270.0 540.0 2.5 2.5 2.5 2.5 2.5 60.0 120.0 60.0 120.0 71.4 120.0 62.5 120.0 60.0 120.0
1001_000 1001_001 1001_010 1001_011 1001_100 31.3 27.8 50.0 50.0 8 8 250.0 400.0 222.2 400.0
Reserved Reserved Reserved 4 4.5 250.0 400.0 250.0 450.0 4 4 62.5 100.0 55.6 100.0
1010_000
Reserved
MOTOROLA
MPC8280 Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
33
Clock Configuration Modes Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=1)1 (Continued)
Mode2 MODCK_HMODCK[1-3] 1010_001 1010_010 1010_011 1010_100 PCI Clock3 (MHz) low 25.0 26.8 25.0 25.0 high 50.0 50.0 50.0 50.0 CPM Multiplication Factor4 8 8 8 8 CPM Clock3 (MHz) low high CPU Multiplication Factor5 3 3.5 4 4.5 CPU Clock3 (MHz) low high Bus Division Factor 3 3 3 3 Bus Clock3,6 (MHz) low high
200.0 400.0 214.3 400.0 200.0 400.0 200.0 400.0
200.0 400.0 250.0 466.7 266.7 533.3 300.0 600.0
66.7 133.3 71.4 133.3 66.7 133.3 66.7 133.3
1011_000 1011_001 1011_010 1011_011 1011_100 25.0 25.0 25.0 25.0 50.0 50.0 50.0 50.0 8 8 8 8 200.0 400.0 200.0 400.0 200.0 400.0 200.0 400.0
Reserved 2.5 3 3.5 4 200.0 400.0 240.0 480.0 280.0 560.0 320.0 640.0 2.5 2.5 2.5 2.5 80.0 160.0 80.0 160.0 80.0 160.0 80.0 160.0
1100_101 1100_110 1100_111 1101_000
31.3 27.8 25.0 25.0
50.0 50.0 50.0 50.0
6 6 6 6
187.5 300.0 166.7 300.0 150.0 300.0 150.0 300.0
4 4.5 5 5.5
250.0 400.0 250.0 450.0 250.0 500.0 275.0 550.0
3 3 3 3
62.5 100.0 55.6 100.0 50.0 100.0 50.0 100.0
1101_001 1101_010 1101_011 1101_100
29.8 26.0 25.0 25.0
50.0 50.0 50.0 50.0
6 6 6 6
178.6 300.0 156.3 300.0 150.0 300.0 150.0 300.0
3.5 4 4.5 5
250.0 420.0 250.0 480.0 270.0 540.0 300.0 600.0
2.5 2.5 2.5 2.5
71.4 120.0 62.5 120.0 60.0 120.0 60.0 120.0
1110_000 1110_001 1110_010 1110_011
25.0 25.0 28.6 25.0
50.0 50.0 50.0 50.0
5 5 5 5
125.0 250.0 125.0 250.0 142.9 250.0 125.0 250.0
2.5 3 3.5 4
156.3 312.5 187.5 375.0 250.0 437.5 250.0 500.0
2 2 2 2
62.5 125.0 62.5 125.0 71.4 125.0 62.5 125.0
1110_100 1110_101 1110_110 1110_111
37.5 33.3 30.0 27.3
50.0 50.0 50.0 50.0
5 5 5 5
187.5 250.0 166.7 250.0 150.0 250.0 136.4 250.0
4 4.5 5 5.5
250.0 333.3 250.0 375.0 250.0 416.7 250.0 458.3
3 3 3 3
62.5 55.6 50.0 45.5
83.3 83.3 83.3 83.3
34
MPC8280 Hardware Specifications
MOTOROLA
Pinout Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=1)1 (Continued)
Mode2 MODCK_HMODCK[1-3] PCI Clock3 (MHz) low high CPM Multiplication Factor4 CPM Clock3 (MHz) low high CPU Multiplication Factor5 CPU Clock3 (MHz) low high Bus Division Factor Bus Clock3,6 (MHz) low high
1100_000 1100_001 1100_010
1 2 3 4 5 6
25.0 25.0 25.0
50.0 50.0 50.0
4 6 6
100.0 200.0 150.0 300.0 150.0 300.0
Bypass Bypass Bypass
50.0 100.0 60.0 120.0 50.0 100.0
2 2.5 3
50.0 100.0 60.0 120.0 50.0 100.0
As shown in Table 13, PCI_MODCK determines the PCI clock frequency range. Refer to Table 17 for higher range configurations. MODCK_H = hard reset configuration word [28-31]. Refer to Section 5.4 in the MPC8260 User's Manual; MODCK[1-3] = three hardware configuration pins. `High' and `low' indicate frequency limits for a given configuration. CPM multiplication factor = CPM clock/bus clock CPU multiplication factor = Core PLL multiplication factor 60x and local bus frequency. Identical to CLKIN.
1.4
1.4.1
Pinout
ZU Package--MPC8280 and MPC8270
This section provides the pin assignments and pinout lists for both HiP7 PowerQUICC II packages.
The following figures and table represent the standard 480 TBGA package. For information on the alternate package for the MPC8280 and the MPC8270, refer to Section 1.4.2, "VR Package--MPC8275VR and MPC8270VR" on page 49.
1.4.1.1
ZU Pin Assignments
Figure 12 shows the pinout of the ZU package as viewed from the top surface.
MOTOROLA
MPC8280 Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
35
Pinout
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ 1
2
3
456
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ
2
3
456
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Not to Scale
Figure 12. Pinout of the 480 TBGA Package (View from Top)
Figure 13 shows the side profile of the TBGA package to indicate the direction of the top surface view.
View
Copper Heat Spreader (Oxidized for Insulation) Polymide Tape Die Soldermask Glob-Top Filled Area Glob-Top Dam 1.27 mm Pitch Wire Bonds Copper Traces Die Attach Etched Cavity Pressure Sensitive Adhesive
Figure 13. Side View of the TBGA Package
36
MPC8280 Hardware Specifications
MOTOROLA
Pinout
Table 19 shows the pinout list of the MPC8280 and MPC8270. Table 20 defines conventions and acronyms used in Table 19.
Table 19. MPC8280 and MPC8270 Pinout List
Pin Name Ball MPC8280/MPC8270 BR BG ABB/IRQ2 TS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 MPC8280 only (UTOPIA Pins) W5 F4 E2 E3 G1 H5 H2 H1 J5 J4 J3 J2 J1 K4 K3 K2 K1 L5 L4 L3 L2 L1 M5 N5 N4 N3 N2 N1 P4 P3 P2 P1
MOTOROLA
MPC8280 Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
37
Pinout Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name Ball MPC8280/MPC8270 A28 A29 A30 A31 TT0 TT1 TT2 TT3 TT4 TBST TSIZ0 TSIZ1 TSIZ2 TSIZ3 AACK ARTRY DBG DBB/IRQ3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 MPC8280 only (UTOPIA Pins) R1 R3 R5 R4 F1 G4 G3 G2 F2 D3 C1 E4 D2 F5 F3 E1 V1 V2 B20 A18 A16 A13 E12 D9 A6 B5 A20 E17 B15 B13 A11 E9 B7 B4
38
MPC8280 Hardware Specifications
MOTOROLA
Pinout Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name Ball MPC8280/MPC8270 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 MPC8280 only (UTOPIA Pins) D19 D17 D15 C13 B11 A8 A5 C5 C19 C17 C15 D13 C11 B8 A4 E6 E18 B17 A15 A12 D11 C8 E7 A3 D18 A17 A14 B12 A10 D8 B6 C4 C18 E16
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MPC8280 Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
39
Pinout Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name Ball MPC8280/MPC8270 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 DP0/RSRV/EXT_BR2 IRQ1/DP1/EXT_BG2 IRQ2/DP2/TLBISYNC/EXT_DBG2 IRQ3/DP3/CKSTP_OUT/EXT_BR3 IRQ4/DP4/CORE_SRESET/EXT_BG3 IRQ5/DP5/TBEN/EXT_DBG3 IRQ6/DP6/CSE0 IRQ7/DP7/CSE1 PSDVAL TA TEA GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5 CPU_DBG CPU_BR CS0 CS1 MPC8280 only (UTOPIA Pins) B14 C12 B10 A7 C6 D5 B18 B16 E14 D12 C10 E8 D6 C2 B22 A22 E21 D21 C21 B21 A21 E20 V3 C22 V5 W1 U2 U3 Y4 U4 R2 Y3 F25 C29
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MPC8280 Hardware Specifications
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Pinout Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name Ball MPC8280/MPC8270 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10/BCTL1 CS11/AP0 BADDR27 BADDR28 ALE BCTL0 PWE0/PSDDQM0/PBS0 PWE1/PSDDQM1/PBS1 PWE2/PSDDQM2/PBS2 PWE3/PSDDQM3/PBS3 PWE4/PSDDQM4/PBS4 PWE5/PSDDQM5/PBS5 PWE6/PSDDQM6/PBS6 PWE7/PSDDQM7/PBS7 PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 LWE0/LSDDQM0/LBS0/PCI_CFG0 LWE1/LSDDQM1/LBS1/PCI_CFG1 LWE2/LSDDQM2/LBS2/PCI_CFG2 LWE3/LSDDQM3/LBS3/PCI_CFG3 LSDA10/LGPL0/PCI_MODCKH0 LSDWE/LGPL1/PCI_MODCKH1 MPC8280 only (UTOPIA Pins) E27 E28 F26 F27 F28 G25 D29 E29 F29 G28 T5 U1 T2 A27 C25 E24 D24 C24 B26 A26 B25 A25 E23 B24 A24 B23 A23 D22 H28 H27 H26 G29 D27 C28
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41
Pinout Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name Ball MPC8280/MPC8270 LOE/LSDRAS/LGPL2/PCI_MODCKH2 LSDCAS/LGPL3/PCI_MODCKH3 LGTA/LUPMWAIT/LGPL4/LPBS LGPL5/LSDAMUX/PCI_MODCK LWR L_A14/PAR L_A15/FRAME/SMI L_A16/TRDY L_A17/IRDY/CKSTP_OUT L_A18/STOP L_A19/DEVSEL L_A20/IDSEL L_A21/PERR L_A22/SERR L_A23/REQ0 L_A24/REQ1/HSEJSW L_A25/GNT0 L_A26/GNT1/HSLED L_A27/GNT2/HSENUM L_A28/RST/CORE_SRESET L_A29/INTA L_A30/REQ2 L_A31/DLLOUT LCL_D0/AD0 LCL_D1/AD1 LCL_D2/AD2 LCL_D3/AD3 LCL_D4/AD4 LCL_D5/AD5 LCL_D6/AD6 LCL_D7/AD7 LCL_D8/AD8 LCL_D9/AD9 LCL_D10/AD10 MPC8280 only (UTOPIA Pins) E26 D25 C26 B27 D28 N27 T29 R27 R26 R29 R28 W29 P28 N26 AA27 P29 AA26 N25 AA25 AB29 AB28 P25 AB27 H29 J29 J28 J27 J26 J25 K25 L29 L27 L26 L25
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MPC8280 Hardware Specifications
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Pinout Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name Ball MPC8280/MPC8270 LCL_D11/AD11 LCL_D12/AD12 LCL_D13/AD13 LCL_D14/AD14 LCL_D15/AD15 LCL_D16/AD16 LCL_D17/AD17 LCL_D18/AD18 LCL_D19/AD19 LCL_D20/AD20 LCL_D21/AD21 LCL_D22/AD22 LCL_D23/AD23 LCL_D24/AD24 LCL_D25/AD25 LCL_D26/AD26 LCL_D27/AD27 LCL_D28/AD28 LCL_D29/AD29 LCL_D30/AD30 LCL_D31/AD31 LCL_DP0/C0/BE0 LCL_DP1/C1/BE1 LCL_DP2/C2/BE2 LCL_DP3/C3/BE3 IRQ0/NMI_OUT IRQ7/INT_OUT/APE TRST TCK TMS TDI TDO TRIS PORESET MPC8280 only (UTOPIA Pins) M29 M28 M27 M26 N29 T25 U27 U26 U25 V29 V28 V27 V26 W27 W26 W25 Y29 Y28 Y25 AA29 AA28 L28 N28 T28 W28 T1 D1 AH3 AG5 AJ3 AE6 AF5 AB4 AG6
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43
Pinout Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name Ball MPC8280/MPC8270 HRESET SRESET QREQ RSTCONF MODCK1/AP1/TC0/BNKSEL0 MODCK2/AP2/TC1/BNKSEL1 MODCK3/AP3/TC2/BNKSEL2 CLKIN1 PA0/RESTART1/DREQ3 PA1/REJECT1/DONE3 PA2/CLK20/DACK3 PA3/CLK19/DACK4/L1RXD1A2 PA4/REJECT2/DONE4 PA5/RESTART2/DREQ4 PA6 PA7/SMSYN2 PA8/SMRXD2 PA9/SMTXD2 PA10/MSNUM5 PA11/MSNUM4 PA12/MSNUM3 PA13/MSNUM2 PA14/FCC1_RXD3 PA15/FCC1_RXD2 PA16/FCC1_RXD1 PA17/FCC1_RXD0/FCC1_RXD PA18/FCC1_TXD0/FCC1_TXD PA19/FCC1_TXD1 PA20/FCC1_TXD2 PA21/FCC1_TXD3 FCC2_UTM_TXADDR2 FCC2_UTM_TXADDR1 FCC2_UTM_TXADDR0 FCC2_UTM_RXADDR0 FCC2_UTM_RXADDR1 FCC2_UTM_RXADDR2 L1RSYNCA1 L1TSYNCA1/L1GNTA1 L1RXD0A1/L1RXDA1 L1TXD0A1 FCC1_UT8_RXD0/FCC1_UT16_RXD8 FCC1_UT8_RXD1/FCC1_UT16_RXD9 FCC1_UT8_RXD2/ FCC1_UT16_RXD10 FCC1_UT8_RXD3/ FCC1_UT16_RXD11 FCC1_UT8_RXD4/ FCC1_UT16_RXD12 /FCC1_UT8_RXD5/ FCC1_UT16_RXD13 FCC1_UT8_RXD6/ FCC1_UT16_RXD14 FCC1_UT8_RXD7/ FCC1_UT16_RXD15 FCC1_UT8_TXD7/FCC1_UT16_TXD15 FCC1_UT8_TXD6/FCC1_UT16_TXD14 FCC1_UT8_TXD5/FCC1_UT16_TXD13 FCC1_UT8_TXD4/FCC1_UT16_TXD12 MPC8280 only (UTOPIA Pins) AH5 AF6 AA3 AJ4 W2 W3 W4 AH4 AC29 AC25 AE28 AG29 AG28 AG26 AE24 AH25 AF23 AH23 AE22 AH22 AJ21 AH20 AG19 AF18 AF17 AE16 AJ16 AG15 AJ13 AE13
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MPC8280 Hardware Specifications
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Pinout Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name Ball MPC8280/MPC8270 PA22 PA23 PA24/MSNUM1 PA25/MSNUM0 PA26/FCC1_MII_RX_ER PA27/FCC1_MII_RX_DV PA28/FCC1_MII_TX_EN PA29/FCC1_MII_TX_ER PA30/FCC1_MII_CRS/FCC1_RTS PA31/FCC1_MII_COL PB4/FCC3_TXD3/L1RSYNCA2/ FCC3_RTS PB5/FCC3_TXD2/L1TSYNCA2/ L1GNTA2 MPC8280 only (UTOPIA Pins) FCC1_UT8_TXD3/FCC1_UT16_TXD11 FCC1_UT8_TXD2/FCC1_UT16_TXD10 /FCC1_UT8_TXD1/FCC1_UT16_TXD9 FCC1_UT8_TXD0/FCC1_UT16_TXD8 FCC1_UTM_RXCLAV/ FCC1_UTS_RXCLAV FCC1_UT_RXSOC FCC1_UTM_RXENB/ FCC1_UTS_RXENB FCC1_UT_TXSOC FCC1_UTM_TXCLAV/ FCC1_UTS_TXCLAV FCC1_UTM_TXENB/ FCC1_UTS_TXENB FCC2_UT8_RXD0 FCC2_UT8_RXD1 AF12 AG11 AH9 AJ8 AH7 AF7 AD5 AF1 AD3 AB5 AD28 AD26 AD25 AE26 AH27 AG24 AH24 AJ24 AG22 AH21 AG20 AF19 AJ18 AJ17 AE14 AF13 AG12
PB6/FCC3_TXD1/L1RXDA2/L1RXD0A2 FCC2_UT8_RXD2 PB7/FCC3_TXD0/FCC3_TXD/ L1TXDA2/L1TXD0A2 PB8/FCC3_RXD0/FCC3_RXD/TXD3 PB9/FCC3_RXD1/L1TXD2A2 PB10/FCC3_RXD2 PB11/FCC3_RXD3 PB12/FCC3_MII_CRS/TXD2 PB13/FCC3_MII_COL/L1TXD1A2 PB14/FCC3_MII_TX_EN/RXD3 PB15/FCC3_MII_TX_ER/RXD2 PB16/FCC3_MII_RX_ER/CLK18 PB17/FCC3_MII_RX_DV/CLK17 PB18/FCC2_RXD3/L1CLKOD2/ L1RXD2A2 FCC2_UT8_RXD3 FCC2_UT8_TXD3/L1RSYNCD1 FCC2_UT8_TXD2/L1TSYNCD1/ L1GNTD1 FCC2_UT8_TXD1/L1RXDD1 FCC2_UT8_TXD0/L1TXDD1 L1CLKOB1/L1RSYNCC1 L1RQB1/L1TSYNCC1/L1GNTC1 L1RXDC1 L1TXDC1 L1CLKOA1 L1RQA1 FCC2_UT8_RXD4
PB19FCC2_RXD2/L1RQD2/L1RXD3A2 FCC2_UT8_RXD5 PB20/FCC2_RXD1/L1RSYNCD2/ L1TXD1A1 FCC2_UT8_RXD6
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Pinout Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name Ball MPC8280/MPC8270 PB21/FCC2_RXD0/FCC2_RXD/ L1TSYNCD2/L1GNTD2 PB22/FCC2_TXD0/FCC2_TXD/ L1RXDD2 PB23/FCC2_TXD1/L1TXDD2 PB24/FCC2_TXD2/L1RSYNCC2 PB25/FCC2_TXD3/L1TSYNCC2/ L1GNTC2 PB26/FCC2_MII_CRS/L1RXDC2 PB27/FCC2_MII_COL/L1TXDC2 PB28/FCC2_MII_RX_ER/FCC2_RTS/ L1TSYNCB2/L1GNTB2/TXD1 PB29/L1RSYNCB2/ FCC2_MII_TX_EN PB30/FCC2_MII_RX_DV/L1RXDB2 PB31/FCC2_MII_TX_ER/L1TXDB2 PC0/DREQ1/BRGO7/SMSYN2/ L1CLKOA2 PC1/DREQ2/BRGO6/L1RQA2 PC2/FCC3_CD/DONE2 PC3/FCC3_CTS/DACK2/CTS4 PC4/SI2_L1ST4/FCC2_CD PC5/SI2_L1ST3/FCC2_CTS PC6/FCC1_CD FCC2_UT8_TXD3 FCC2_UT8_TXD2 FCC2_UTM_RXENB/ FCC2_UTS_RXENB FCC2_UTM_TXCLAV/ FCC2_UTS_TXCLAV L1CLKOC1/FCC1_UTM_RXADDR2/ FCC1_UTS_RXADDR2/ FCC1_UTM_RXCLAV1 L1RQC1/FCC1_UTM_TXADDR2/ FCC1_UTS_TXADDR2/ FCC1_UTM_TXCLAV1 FCC1_UT16_TXD0 FCC1_UT16_TXD1 FCC1_UT16_TXD2/SI1_L1ST4/ FCC2_UT8_RXD3 L1CLKOD1/FCC2_UT8_RXD2 SI1_L1ST3/FCC1_UTM_RXADDR1/ FCC1_UTS_RXADDR1 FCC2_UTM_RXCLAV/ FCC2_UTS_RXCLAV FCC2_UT_TXSOC FCC2_UT_RXSOC MPC8280 only (UTOPIA Pins) FCC2_UT8_RXD7/L1TXD2A1 FCC2_UT8_TXD7/L1RXD1A1 FCC2_UT8_TXD6/L1RXD2A1 FCC2_UT8_TXD5/L1RXD3A1 FCC2_UT8_TXD4/L1TXD3A1 FCC2_UT8_TXD1 FCC2_UT8_TXD0 AH11 AH16 AE15 AJ9 AE9 AJ7 AH6 AE3 AE2 AC5 AC4 AB26 AD29 AE29 AE27 AF27 AF24 AJ26
PC7/FCC1_CTS
AJ25
PC8/CD4/RENA4/SI2_L1ST2/CTS3 PC9/CTS4/CLSN4/SI2_L1ST1/ L1TSYNCA2/L1GNTA2 PC10/CD3/RENA3 PC11/CTS3/CLSN3/L1TXD3A2 PC12/CD2/RENA2
AF22 AE21 AF20 AE19 AE18
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MPC8280 Hardware Specifications
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Pinout Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name Ball MPC8280/MPC8270 PC13/CTS2/CLSN2 PC14/CD1/RENA1 PC15/CTS1/CLSN1/SMTXD2 PC16/CLK16/TIN4 PC17/CLK15/TIN3/BRGO8 PC18/CLK14/TGATE2 PC19/CLK13/BRGO7 PC20/CLK12/TGATE1 PC21/CLK11/BRGO6 PC22/CLK10/DONE1 PC23/CLK9/BRGO5/DACK1 PC24/CLK8/TOUT4 PC25/CLK7/BRGO4 PC26/CLK6/TOUT3/TMCLK PC27/FCC3_TXD/FCC3_TXD0/CLK5/ BRGO3 PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2 PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1 PC30/CLK2/TOUT1 PC31/CLK1/BRGO1 PD4/BRGO8/FCC3_RTS/SMRXD2 PD5/DONE1 PD6/DACK1 PD7/SMSYN1/FCC1_TXCLAV2 PD8/SMRXD1/BRGO5 PD9/SMTXD1/BRGO3 PD10/L1CLKOB2/BRGO4 PD11/L1RQB2 PD12 PD13 PD14/L1CLKOC2/I2CSCL L1TSYNCD1/L1GNTD1 FCC1_UT16_TXD3 FCC1_UT16_TXD4 FCC1_UTM_TXADDR3/ FCC1_UTS_TXADDR3 FCC2_UT_TXPRTY FCC2_UT_RXPRTY FCC2_UT8_RXD1/L1RSYNCB1 FCC2_UT8_RXD0/L1TSYNCB1/ L1GNTB1 SI1_L1ST2/L1RXDB1 SI1_L1ST1/L1TXDB1 FCC1_UT16_RXD0 FCC2_UT8_TXD3 FCC2_UT8_TXD3 FCC2_UT8_TXD2 MPC8280 only (UTOPIA Pins) L1RQD1/FCC1_UTM_TXADDR1/ FCC1_UTS_TXADDR1 FCC1_UTM_RXADDR0/ FCC1_UTS_RXADDR0 FCC1_UTM_TXADDR0/ FCC1_UTS_TXADDR0 AH18 AH17 AG16 AF15 AJ15 AH14 AG13 AH12 AJ11 AG10 AE10 AF9 AE8 AJ6 AG2 AF3 AF2 AE1 AD1 AC28 AD27 AF29 AF28 AG25 AH26 AJ27 AJ23 AG23 AJ22 AE20
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Pinout Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name Ball MPC8280/MPC8270 PD15/L1RQC2/I2CSDA PD16/SPIMISO PD17/BRGO2/SPIMOSI PD18/SPICLK MPC8280 only (UTOPIA Pins) FCC1_UT16_RXD1 FCC1_UT_TXPRTY/L1TSYNCC1/ L1GNTC1 FCC1_UT_RXPRTY FCC1_UTM_RXADDR4/ FCC1_UTS_RXADDR4/ FCC1_UTM_RXCLAV3 FCC1_UTM_TXADDR4/ FCC1_UTS_TXADDR4/ FCC1_UTM_TXCLAV3 FCC1_UT16_RXD2 FCC1_UT16_RXD3 FCC1_UT16_TXD5 FCC1_UT16_RXD4/L1RSYNCD1 FCC1_UT16_RXD5/L1RXDD1 FCC1_UT16_TXD6/L1TXDD1 FCC1_UT16_RXD6/L1RSYNCC1 FCC1_UT16_RXD7/L1RXDC1 FCC1_UT16_TXD7/L1TXDC1 FCC1_UTM_RXADDR3/ FCC1_UTS_RXADDR3/ FCC1_UTM_RXCLAV2 FCC2_UTM_TXENB/ FCC2_UTS_TXENB AJ20 AG18 AG17 AF16
PD19/SPISEL/BRGO1
AH15
PD20/RTS4/TENA4/L1RSYNCA2 PD21/TXD4/L1RXD0A2/L1RXDA2 PD22/RXD4L1TXD0A2/L1TXDA2 PD23/RTS3/TENA3 PD24/TXD3 PD25/RXD3 PD26/RTS2/TENA2 PD27/TXD2 PD28/RXD2 PD29/RTS1/TENA1
AJ14 AH13 AJ12 AE12 AF10 AG9 AH8 AG7 AE4 AG1
PD30/TXD1 PD31/RXD1 VCCSYN VCCSYN1 CLKIN2 SPARE41 PCI_MODE2 SPARE61 THERMAL03 THERMAL13
AD4 AD2 AB3 B9 AE11 U5 AF25 V4 AA1 AG4
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MPC8280 Hardware Specifications
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Pinout Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name Ball MPC8280/MPC8270 I/O power MPC8280 only (UTOPIA Pins) AG21, AG14, AG8, AJ1, AJ2, AH1, AH2, AG3, AF4, AE5, AC27, Y27, T27, P27, K26, G27, AE25, AF26, AG27, AH28, AH29, AJ28, AJ29, C7, C14, C16, C20, C23, E10, A28, A29, B28, B29, C27, D26, E25, H3, M4, T3, AA4, A1, A2, B1, B2, C3, D4, E5 U28, U29, K28, K29, A9, A19, B19, M1, M2, Y1, Y2, AC1, AC2, AH19, AJ19, AH10, AJ10, AJ5 AA5, AB14, AB25, AF21, AF14, AF8, AE7, AF11, AE17, AE23, AC26, AB25, Y26, V25, T26, R25, P26, M25, K27, H25, G26, D7, D10, D14, D16, D20, D23, C9, E11, E13, E15, E19, E22, B3, G5, H4, K5, M3, P5, T4, Y5, AA2, AC3
Core Power
Ground
1 2
Must be pulled down or left floating. If PCI is not desired, must be pulled up or left floating. 3 For information on how to use this pin, refer to MPC8260 PowerQUICC II Thermal Resistor Guide (AN2271/D). 4 GNDSYN (AB1): This pin exists as a separate ground signal in MPC826x(A) devices; it does not exist as a separate ground signal on the MPC8280. New designs must connect AB1 to GND and follow the suggestions in Section 1.2.2.1, "Layout Practices." Old designs in which the MPC8280 is used as a drop-in replacement can leave the pin connected to GND with the noise filtering capacitors. 5 XFC (AB2) pin: This pin is used in MPC826x(A) devices; it is not used in MPC8280 because there is no need for external capacitor to operate the PLL. New designs should connect AB2 (XFC) pin to GND. Old designs in which the MPC8280 is used as a drop-in replacement can leave the pin connected to the current capacitor.
Symbols used in Table 19 are described in Table 20.
Table 20. Symbol Legend
Symbol OVERBAR UTM UTS UT8 UT16 MII Meaning Signals with overbars, such as TA, are active low. Indicates that a signal is part of the UTOPIA master interface. Indicates that a signal is part of the UTOPIA slave interface. Indicates that a signal is part of the 8-bit UTOPIA interface. Indicates that a signal is part of the 16-bit UTOPIA interface. Indicates that a signal is part of the media independent interface.
1.4.2
VR Package--MPC8275VR and MPC8270VR
The following figures and table represent the alternate 516 PBGA package. For information on the standard package for the MPC8280 and the MPC8270, refer to Section 1.4.1, "ZU Package--MPC8280 and MPC8270" on page 35.
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Pinout
1.4.2.1
VR Pin Assignments
1 2 3 456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1 2 3 456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Figure 14 shows the pinout of the VR package as viewed from the top surface.
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
Not to Scale
Figure 14. Pinout of the 516 PBGA Package (View from Top)
Figure 15 shows the side profile of the PBGA package to indicate the direction of the top surface view.
Transfer molding compound
Plated substrate via
Die attach
1.0 mil Au wire
Ball bond Screen-printed solder mask Cu substrate traces
DIE
1 mm pitch
BT resin glass epoxy
Figure 15. Side View of the PBGA Package
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MPC8280 Hardware Specifications
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Pinout
Table 21 shows the pinout list of the MPC8275VR and MPC8270VR. Table 20 defines conventions and acronyms used in Table 21.
Table 21. MPC8275VR and MPC8270VR Pinout List
Pin Name Ball MPC8275VR/MPC8270VR BR BG ABB/IRQ2 TS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 MPC8275VR only (UTOPIA Pins) C16 D2 C1 D1 D5 E8 C4 B4 A4 D7 D8 C6 B5 B6 C7 C8 A6 D9 F11 B7 B8 C9 A7 B9 E11 A8 D11 B10 C11 A9 B11 C12
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Pinout Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name Ball MPC8275VR/MPC8270VR A28 A29 A30 A31 TT0 TT1 TT2 TT3 TT4 TBST TSIZ0 TSIZ1 TSIZ2 TSIZ3 AACK ARTRY DBG DBB/IRQ3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 MPC8275VR only (UTOPIA Pins) D12 A10 B12 B13 E7 B3 F8 A3 C3 F5 E3 E2 E1 E4 D3 C2 A14 C15 W4 Y1 V1 P4 N3 K5 J4 G1 AB1 U4 U2 N6 N1 L1 J5 G3
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MPC8280 Hardware Specifications
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Pinout Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name Ball MPC8275VR/MPC8270VR D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 MPC8275VR only (UTOPIA Pins) AA2 W1 T3 T1 M2 K2 J1 G4 U5 T5 P5 P3 M3 K3 H2 G5 AA1 V2 U1 P2 M4 K4 H3 F2 Y2 U3 T2 N2 M5 K1 H4 F1 W2 T4
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Pinout Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name Ball MPC8275VR/MPC8270VR D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 DP0/RSRV/EXT_BR2 IRQ1/DP1/EXT_BG2 IRQ2/DP2/TLBISYNC/EXT_DBG2 IRQ3/DP3/CKSTP_OUT/EXT_BR3 IRQ4/DP4/CORE_SRESET/EXT_BG3 IRQ5/DP5/TBEN/EXT_DBG3 IRQ6/DP6/CSE0 IRQ7/DP7/CSE1 PSDVAL TA TEA GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5 CPU_DBG CPU_BR CS0 CS1 MPC8275VR only (UTOPIA Pins) R3 N4 M1 J2 H5 F3 V3 R5 R2 N5 L2 J3 H1 F4 AB3 W5 AC2 AA3 AD1 AC1 AB2 Y3 D15 Y4 D16 E15 D14 E14 A17 B14 F13 B17 AC6 AD6
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MPC8280 Hardware Specifications
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Pinout Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name Ball MPC8275VR/MPC8270VR CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10/BCTL1 CS11/AP0 BADDR27 BADDR28 ALE BCTL0 PWE0/PSDDQM0/PBS0 PWE1/PSDDQM1/PBS1 PWE2/PSDDQM2/PBS2 PWE3/PSDDQM3/PBS3 PWE4/PSDDQM4/PBS4 PWE5/PSDDQM5/PBS5 PWE6/PSDDQM6/PBS6 PWE7/PSDDQM7/PBS7 PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 LWE0/LSDDQM0/LBS0/PCI_CFG0 LWE1/LSDDQM1/LBS1/PCI_CFG1 LWE2/LSDDQM2/LBS2/PCI_CFG2 LWE3/LSDDQM3/LBS3/PCI_CFG3 LSDA10/LGPL0/PCI_MODCKH0 LSDWE/LGPL1/PCI_MODCKH1 MPC8275VR only (UTOPIA Pins) AE6 AB7 AF7 AC7 AD7 AF8 AE8 AD8 AC8 AB8 C13 A12 D13 AF4 AA5 AE4 AD4 AF3 AB4 AE3 AF2 AD3 AE2 AD2 AE1 AC3 W6 AA4 AC9 AD9 AE9 AF9 AB6 AF5
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Pinout Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name Ball MPC8275VR/MPC8270VR LOE/LSDRAS/LGPL2/PCI_MODCKH2 LSDCAS/LGPL3/PCI_MODCKH3 LGTA/LUPMWAIT/LGPL4/LPBS LGPL5/LSDAMUX/PCI_MODCK LWR L_A14/PAR L_A15/FRAME/SMI L_A16/TRDY L_A17/IRDY/CKSTP_OUT L_A18/STOP L_A19/DEVSEL L_A20/IDSEL L_A21/PERR L_A22/SERR L_A23/REQ0 L_A24/REQ1/HSEJSW L_A25/GNT0 L_A26/GNT1/HSLED L_A27/GNT2/HSENUM L_A28/RST/CORE_SRESET L_A29/INTA L_A30/REQ2 L_A31/DLLOUT LCL_D0/AD0 LCL_D1/AD1 LCL_D2/AD2 LCL_D3/AD3 LCL_D4/AD4 LCL_D5/AD5 LCL_D6/AD6 LCL_D7/AD7 LCL_D8/AD8 LCL_D9/AD9 LCL_D10/AD10 MPC8275VR only (UTOPIA Pins) AE5 AD5 AC5 AB5 AF6 AE13 AD15 AF16 AF15 AE15 AE14 AC17 AD14 AF13 AE20 AC14 AC19 AD13 AF21 AF22 AE21 AB14 AD20 AB9 AB10 AC10 AD10 AE10 AF10 AF11 AB12 AB11 AF12 AE11
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Pinout Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name Ball MPC8275VR/MPC8270VR LCL_D11/AD11 LCL_D12/AD12 LCL_D13/AD13 LCL_D14/AD14 LCL_D15/AD15 LCL_D16/AD16 LCL_D17/AD17 LCL_D18/AD18 LCL_D19/AD19 LCL_D20/AD20 LCL_D21/AD21 LCL_D22/AD22 LCL_D23/AD23 LCL_D24/AD24 LCL_D25/AD25 LCL_D26/AD26 LCL_D27/AD27 LCL_D28/AD28 LCL_D29/AD29 LCL_D30/AD30 LCL_D31/AD31 LCL_DP0/C0/BE0 LCL_DP1/C1/BE1 LCL_DP2/C2/BE2 LCL_DP3/C3/BE3 IRQ0/NMI_OUT IRQ7/INT_OUT/APE TRST TCK TMS TDI TDO TRIS PORESET MPC8275VR only (UTOPIA Pins) AC13 AC12 AB13 AD12 AF14 AF17 AE16 AD16 AC16 AB16 AF18 AE17 AD17 AB17 AE18 AD18 AC18 AE19 AF20 AD19 AB18 AE12 AA13 AC15 AF19 A11 E5 F22 A24 C24 A25 B24 C19 B25
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Pinout Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name Ball MPC8275VR/MPC8270VR HRESET SRESET QREQ RSTCONF MODCK1/AP1/TC0/BNKSEL0 MODCK2/AP2/TC1/BNKSEL1 MODCK3/AP3/TC2/BNKSEL2 CLKIN1 PA0/RESTART1/DREQ3 PA1/REJECT1/DONE3 PA2/CLK20/DACK3 PA3/CLK19/DACK4/L1RXD1A2 PA4/REJECT2/DONE4 PA5/RESTART2/DREQ4 PA6 PA7/SMSYN2 PA8/SMRXD2 PA9/SMTXD2 PA10/MSNUM5 PA11/MSNUM4 PA12/MSNUM3 PA13/MSNUM2 PA14/FCC1_RXD3 PA15/FCC1_RXD2 PA16/FCC1_RXD1 PA17/FCC1_RXD0/FCC1_RXD PA18/FCC1_TXD0/FCC1_TXD PA19/FCC1_TXD1 PA20/FCC1_TXD2 PA21/FCC1_TXD3 FCC2_UTM_TXADDR2 FCC2_UTM_TXADDR1 FCC2_UTM_TXADDR0 FCC2_UTM_RXADDR0 FCC2_UTM_RXADDR1 FCC2_UTM_RXADDR2 L1RSYNCA1 L1TSYNCA1/L1GNTA1 L1RXD0A1/L1RXDA1 L1TXD0A1 FCC1_UT8_RXD0/FCC1_UT16_RXD8 FCC1_UT8_RXD1/FCC1_UT16_RXD9 FCC1_UT8_RXD2/ FCC1_UT16_RXD10 FCC1_UT8_RXD3/ FCC1_UT16_RXD11 FCC1_UT8_RXD4/ FCC1_UT16_RXD12 /FCC1_UT8_RXD5/ FCC1_UT16_RXD13 FCC1_UT8_RXD6/ FCC1_UT16_RXD14 FCC1_UT8_RXD7/ FCC1_UT16_RXD15 FCC1_UT8_TXD7/FCC1_UT16_TXD15 FCC1_UT8_TXD6/FCC1_UT16_TXD14 FCC1_UT8_TXD5/FCC1_UT16_TXD13 FCC1_UT8_TXD4/FCC1_UT16_TXD12 MPC8275VR only (UTOPIA Pins) D24 E23 D18 E24 B16 F16 A15 G22 AC20 AC21 AF25 AE24 AA21 AD25 AC24 AA22 AA23 Y26 W22 W23 V26 V25 T22 T25 R24 P22 N26 N23 K26 L23
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Pinout Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name Ball MPC8275VR/MPC8270VR PA22 PA23 PA24/MSNUM1 PA25/MSNUM0 PA26/FCC1_MII_RX_ER PA27/FCC1_MII_RX_DV PA28/FCC1_MII_TX_EN PA29/FCC1_MII_TX_ER PA30/FCC1_MII_CRS/FCC1_RTS PA31/FCC1_MII_COL PB4/FCC3_TXD3/L1RSYNCA2/ FCC3_RTS PB5/FCC3_TXD2/L1TSYNCA2/ L1GNTA2 MPC8275VR only (UTOPIA Pins) FCC1_UT8_TXD3/FCC1_UT16_TXD11 FCC1_UT8_TXD2/FCC1_UT16_TXD10 /FCC1_UT8_TXD1/FCC1_UT16_TXD9 FCC1_UT8_TXD0/FCC1_UT16_TXD8 FCC1_UTM_RXCLAV/ FCC1_UTS_RXCLAV FCC1_UT_RXSOC FCC1_UTM_RXENB/ FCC1_UTS_RXENB FCC1_UT_TXSOC FCC1_UTM_TXCLAV/ FCC1_UTS_TXCLAV FCC1_UTM_TXENB/ FCC1_UTS_TXENB FCC2_UT8_RXD0 FCC2_UT8_RXD1 K23 H26 F25 D26 D25 C25 C22 B21 A20 A19 AD21 AD22 AC22 AE26 AB23 AC26 AB26 AA25 W26 W25 V24 U24 R22 R23 M23 L24 K24
PB6/FCC3_TXD1/L1RXDA2/L1RXD0A2 FCC2_UT8_RXD2 PB7/FCC3_TXD0/FCC3_TXD/ L1TXDA2/L1TXD0A2 PB8/FCC3_RXD0/FCC3_RXD/TXD3 PB9/FCC3_RXD1/L1TXD2A2 PB10/FCC3_RXD2 PB11/FCC3_RXD3 PB12/FCC3_MII_CRS/TXD2 PB13/FCC3_MII_COL/L1TXD1A2 PB14/FCC3_MII_TX_EN/RXD3 PB15/FCC3_MII_TX_ER/RXD2 PB16/FCC3_MII_RX_ER/CLK18 PB17/FCC3_MII_RX_DV/CLK17 PB18/FCC2_RXD3/L1CLKOD2/ L1RXD2A2 FCC2_UT8_RXD3 FCC2_UT8_TXD3/L1RSYNCD1 FCC2_UT8_TXD2/L1TSYNCD1/ L1GNTD1 FCC2_UT8_TXD1/L1RXDD1 FCC2_UT8_TXD0/L1TXDD1 L1CLKOB1/L1RSYNCC1 L1RQB1/L1TSYNCC1/L1GNTC1 L1RXDC1 L1TXDC1 L1CLKOA1 L1RQA1 FCC2_UT8_RXD4
PB19FCC2_RXD2/L1RQD2/L1RXD3A2 FCC2_UT8_RXD5 PB20/FCC2_RXD1/L1RSYNCD2/ L1TXD1A1 FCC2_UT8_RXD6
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Pinout Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name Ball MPC8275VR/MPC8270VR PB21/FCC2_RXD0/FCC2_RXD/ L1TSYNCD2/L1GNTD2 PB22/FCC2_TXD0/FCC2_TXD/ L1RXDD2 PB23/FCC2_TXD1/L1TXDD2 PB24/FCC2_TXD2/L1RSYNCC2 PB25/FCC2_TXD3/L1TSYNCC2/ L1GNTC2 PB26/FCC2_MII_CRS/L1RXDC2 PB27/FCC2_MII_COL/L1TXDC2 PB28/FCC2_MII_RX_ER/FCC2_RTS/ L1TSYNCB2/L1GNTB2/TXD1 PB29/L1RSYNCB2/ FCC2_MII_TX_EN PB30/FCC2_MII_RX_DV/L1RXDB2 PB31/FCC2_MII_TX_ER/L1TXDB2 PC0/DREQ1/BRGO7/SMSYN2/ L1CLKOA2 PC1/DREQ2/BRGO6/L1RQA2 PC2/FCC3_CD/DONE2 PC3/FCC3_CTS/DACK2/CTS4 PC4/SI2_L1ST4/FCC2_CD PC5/SI2_L1ST3/FCC2_CTS PC6/FCC1_CD FCC2_UT8_TXD3 FCC2_UT8_TXD2 FCC2_UTM_RXENB/ FCC2_UTS_RXENB FCC2_UTM_TXCLAV/ FCC2_UTS_TXCLAV L1CLKOC1/FCC1_UTM_RXADDR2/ FCC1_UTS_RXADDR2/ FCC1_UTM_RXCLAV1 L1RQC1/FCC1_UTM_TXADDR2/ FCC1_UTS_TXADDR2/ FCC1_UTM_TXCLAV1 FCC1_UT16_TXD0 FCC1_UT16_TXD1 FCC1_UT16_TXD2/SI1_L1ST4/ FCC2_UT8_RXD3 L1CLKOD1/FCC2_UT8_RXD2 SI1_L1ST3/FCC1_UTM_RXADDR1/ FCC1_UTS_RXADDR1 FCC2_UTM_RXCLAV/ FCC2_UTS_RXCLAV FCC2_UT_TXSOC FCC2_UT_RXSOC MPC8275VR only (UTOPIA Pins) FCC2_UT8_RXD7/L1TXD2A1 FCC2_UT8_TXD7/L1RXD1A1 FCC2_UT8_TXD6/L1RXD2A1 FCC2_UT8_TXD5/L1RXD3A1 FCC2_UT8_TXD4/L1TXD3A1 FCC2_UT8_TXD1 FCC2_UT8_TXD0 L21 P25 N25 E26 H23 C26 B26 A22 A21 E20 C20 AE22 AA19 AF24 AE25 AB22 AC25 AB25
PC7/FCC1_CTS
AA24
PC8/CD4/RENA4/SI2_L1ST2/CTS3 PC9/CTS4/CLSN4/SI2_L1ST1/ L1TSYNCA2/L1GNTA2 PC10/CD3/RENA3 PC11/CTS3/CLSN3/L1TXD3A2 PC12/CD2/RENA2
Y24 U22 V23 U23 T26
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Pinout Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name Ball MPC8275VR/MPC8270VR PC13/CTS2/CLSN2 PC14/CD1/RENA1 PC15/CTS1/CLSN1/SMTXD2 PC16/CLK16/TIN4 PC17/CLK15/TIN3/BRGO8 PC18/CLK14/TGATE2 PC19/CLK13/BRGO7 PC20/CLK12/TGATE1 PC21/CLK11/BRGO6 PC22/CLK10/DONE1 PC23/CLK9/BRGO5/DACK1 PC24/CLK8/TOUT4 PC25/CLK7/BRGO4 PC26/CLK6/TOUT3/TMCLK PC27/FCC3_TXD/FCC3_TXD0/CLK5/ BRGO3 PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2 PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1 PC30/CLK2/TOUT1 PC31/CLK1/BRGO1 PD4/BRGO8/FCC3_RTS/SMRXD2 PD5/DONE1 PD6/DACK1 PD7/SMSYN1/FCC1_TXCLAV2 PD8/SMRXD1/BRGO5 PD9/SMTXD1/BRGO3 PD10/L1CLKOB2/BRGO4 PD11/L1RQB2 PD12 PD13 PD14/L1CLKOC2/I2CSCL L1TSYNCD1/L1GNTD1 FCC1_UT16_TXD3 FCC1_UT16_TXD4 FCC1_UTM_TXADDR3/ FCC1_UTS_TXADDR3 FCC2_UT_TXPRTY FCC2_UT_RXPRTY FCC2_UT8_RXD1/L1RSYNCB1 FCC2_UT8_RXD0/L1TSYNCB1/ L1GNTB1 SI1_L1ST2/L1RXDB1 SI1_L1ST1/L1TXDB1 FCC1_UT16_RXD0 FCC2_UT8_TXD3 FCC2_UT8_TXD3 FCC2_UT8_TXD2 MPC8275VR only (UTOPIA Pins) L1RQD1/FCC1_UTM_TXADDR1/ FCC1_UTS_TXADDR1 FCC1_UTM_RXADDR0/ FCC1_UTS_RXADDR0 FCC1_UTM_TXADDR0/ FCC1_UTS_TXADDR0 R26 P26 P24 M26 L26 M24 L22 K25 J25 G26 F26 G24 E25 G23 B23 E22 E21 D21 B20 AF23 AE23 AB21 AD23 AD26 Y22 AB24 Y23 AA26 W24 V22
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Pinout Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name Ball MPC8275VR/MPC8270VR PD15/L1RQC2/I2CSDA PD16/SPIMISO PD17/BRGO2/SPIMOSI PD18/SPICLK MPC8275VR only (UTOPIA Pins) FCC1_UT16_RXD1 FCC1_UT_TXPRTY/L1TSYNCC1/ L1GNTC1 FCC1_UT_RXPRTY FCC1_UTM_RXADDR4/ FCC1_UTS_RXADDR4/ FCC1_UTM_RXCLAV3 FCC1_UTM_TXADDR4/ FCC1_UTS_TXADDR4/ FCC1_UTM_TXCLAV3 FCC1_UT16_RXD2 FCC1_UT16_RXD3 FCC1_UT16_TXD5 FCC1_UT16_RXD4/L1RSYNCD1 FCC1_UT16_RXD5/L1RXDD1 FCC1_UT16_TXD6/L1TXDD1 FCC1_UT16_RXD6/L1RSYNCC1 FCC1_UT16_RXD7/L1RXDC1 FCC1_UT16_TXD7/L1TXDC1 FCC1_UTM_RXADDR3/ FCC1_UTS_RXADDR3/ FCC1_UTM_RXCLAV2 FCC2_UTM_TXENB/ FCC2_UTS_TXENB U26 T23 R25 P23
PD19/SPISEL/BRGO1
N22
PD20/RTS4/TENA4/L1RSYNCA2 PD21/TXD4/L1RXD0A2/L1RXDA2 PD22/RXD4L1TXD0A2/L1TXDA2 PD23/RTS3/TENA3 PD24/TXD3 PD25/RXD3 PD26/RTS2/TENA2 PD27/TXD2 PD28/RXD2 PD29/RTS1/TENA1
M25 L25 J26 K22 G25 H24 F24 H22 B22 D22
PD30/TXD1 PD31/RXD1 VCCSYN VCCSYN1 CLKIN2 SPARE41 PCI_MODE2 SPARE61 THERMAL03 THERMAL13 I/O power
C21 E19 D19 K6 K21 C14 AD24 B15 E17 C23 E6, F6, H6, L5, L6, P6, T6, U6, V5, Y5, AA6, AA8, AA10, AA11, AA14, AA16, AA17, AB19, AB20, W21, U21, T21, P21, N21, M22, J22, H21, F21, F19, F17, E16, F14, E13, E12, F10, E10, E9
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Package Description Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name Ball MPC8275VR/MPC8270VR Core Power MPC8275VR only (UTOPIA Pins) L3, V4, W3, AC11, AD11, AB15, U25, T24, J24, H25, F23, B19, D17, C17, D10, C10 B184, A185, A2, B1, B2, A5, C5, C18, D4, D6, G2, L4, P1, R1, R4, AC4, AE7, AC23, Y25, N24, J23, A23, D23, D20, E18, A13, A16, K10, K11, K12, K13, K14, K15, K16, K17, L10, L11, L12, L13, L14, L15, L16, L17, M10, M11, M12, M13, M14, M15, M16, M17, N10, N11, N12, N13, N14, N15, N16, N17, P10, P11, P12, P13, P14, P15, P16, P17, R10, R11,R12, R13, R14, R15, R16, R17, T10, T11, T12, T13, T14, T15, T16, T17, U10, U11, U12, U13, U14, U15, U16, U17
Ground
1 2
Must be pulled down or left floating. If PCI is not desired, must be pulled up or left floating. 3 For information on how to use this pin, refer to MPC8260 PowerQUICC II Thermal Resistor Guide (AN2271/D). 4 GNDSYN (B18): This pin exists as a separate ground signal in MPC826x(A) devices; it does not exist as a separate ground signal on the MPC8275VR/MPC8270VR. New designs must connect B18 to GND and follow the suggestions in Section 1.2.2.1, "Layout Practices." Old designs in which the MPC8275VR/MPC8270VR is used as a drop-in replacement can leave the pin connected to GND with the noise filtering capacitors. 5 XFC (A18) pin: This pin is used in MPC826x(A) devices; it is not used in MPC8275VR/MPC8270VR because there is no need for external capacitor to operate the PLL. New designs should connect A18 (XFC) pin to GND. Old designs in which the MPC8275VR/MPC8270VR is used as a drop-in replacement can leave the pin connected to the current capacitor.
1.5
1.5.1
Package Description
Package Parameters
Table 22. Package Parameters
The following sections provide the package parameters and mechanical dimensions.
Package parameters are provided in Table 22.
Package ZU VR
Devices MPC8280 MPC8270 MPC8275VR MPC8270VR)
Outline (mm) 37.5 x 37.5 27 x 27
Type TBGA PBGA
Interconnects 480 516
Pitch (mm) 1.27 1
Nominal Unmounted Height (mm) 1.55 2.25
MOTOROLA
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Package Description
1.5.2
1.5.2.1
Mechanical Dimensions
ZU Package Dimensions
Figure 16 provides the mechanical dimensions and bottom surface nomenclature of the 480 TBGA package.
Notes: 1. Dimensions and Tolerancing per ASME Y14.5M-1994. 2. Dimensions in millimeters. 3. Dimension b is measured at the maximum solder ball diameter, parallel to primary data A. 4. Primary data A and the seating plane are defined by the spherical crowns of the solder balls. Millimeters Dim Min A A1 A2 A3 b D D1 e E E1 1.45 0.60 0.85 0.25 0.65 Max 1.65 0.70 0.95 -- 0.85
37.50 BSC 35.56 REF 1.27 BSC 37.50 BSC 35.56 REF
Figure 16. Mechanical Dimensions and Bottom Surface Nomenclature--480 TBGA
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MPC8280 Hardware Specifications
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Package Description
1.5.2.2
VR Package Dimensions
Figure 17 provides the mechanical dimensions and bottom surface nomenclature of the 516 PBGA package.
Figure 17. Mechanical Dimensions and Bottom Surface Nomenclature--516 PBGA
MOTOROLA
MPC8280 Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Ordering Information
1.6
Ordering Information
Figure 18 provides an example of the Motorola part numbering nomenclature for the MPC8280. In addition to the processor frequency, the part numbering scheme also consists of a part modifier that indicates any enhancement(s) in the part from the original production design. Each part number also contains a revision code that refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. For more information, contact your local Motorola sales office.
MPC 82XX C ZU XXX X
Product Code Device Number Temperature Range Blank = 0 to 105 C C = -40 to 105 C Die Revision Level Processor Frequency (CPU/CPM/Bus) Package ZU = 480 TBGA VR = 516 PBGA
Figure 18. Motorola Part Number Key Table 23. Document Revision History
Document Revision 0 0.1 0.2 -- Initial public release Table 21, "VR Pinout": Addition of C18 to the Ground (GND) pin list (page 63) Substantive Changes
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MPC8280 Hardware Specifications
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Ordering Information
MOTOROLA
MPC8280 Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC:
Information in this document is provided solely to enable system and software
Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors
implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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